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| features ? high-performance, low-power avr ? 8-bit microcontroller ? advanced risc architecture ? 133 powerful instructions ? mo st single clock cycle execution ? 32 x 8 general purpose working regist ers + peripheral control registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier ? non volatile program and data memories ? 32k/64k/128k bytes of in-system re programmable flash (at90can32/64/128) ? endurance: 10,000 write/erase cycles ? optional boot code section with independent lock bits ? selectable boot size: 1k bytes, 2k bytes, 4k bytes or 8k bytes ? in-system programming by on-c hip boot program (can, uart, ...) ? true read-while-write operation ? 1k/2k/4k bytes eeprom (endurance: 100,000 write/er ase cycles) (a t90can32/ 64/128) ? 2k/4k/4k bytes internal sram (at90can32/64/128) ? up to 64k bytes optional external memory space ? programming lock fo r software security ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the jtag standard ? programming flash (hardware isp), eepr om, lock & fuse bits ? extensive on-chip debug support ? can controller 2.0a & 2.0b - iso 16845 certified (1) ? 15 full message objects with separate identifier tags and masks ? transmit, receive, automatic reply and frame buffer receive modes ? 1mbits/s maximum transfer rate at 8 mhz ? time stamping, ttc & listening mode (spying or autobaud) ? peripheral features ? programmable watchdog timer with on-chip oscillator ? 8-bit synchronous timer/counter-0 ? 10-bit prescaler ? external event counter ? output compare or 8-bit pwm output ? 8-bit asynchronous timer/counter-2 ? 10-bit prescaler ? external event counter ? output compare or 8-bit pwm output ? 32khz oscillator for rtc operation ? dual 16-bit synchronous timer/counters-1 & 3 ? 10-bit prescaler ? input capture with noise canceler ? external event counter ? 3-output compare or 16-bit pwm output ? output compare modulation ? 8-channel, 10-bit sar adc ? 8 single-ended channels ? 7 differential channels ? 2 differential channels with programmable gain at 1x, 10x, or 200x ? on-chip analog comparator ? byte-oriented two-wire serial interface ? dual programmable serial usart ? master/slave spi serial interface ? programming flash (hardware isp) ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated rc oscillator ? 8 external interrupt sources ? 5 sleep modes: idle, adc noise reduction, power-save, power-down & standby ? software selectable clock frequency ? global pull-up disable ? i/o and packages ? 53 programmable i/o lines ? 64-lead tqfp and 64-lead qfn ? operating voltages: 2.7 - 5.5v ? operating temperature: industrial (-40c to +85c) ? maximum frequency: 8 mhz at 2.7v, 16 mhz at 4.5v note: 1. details on section 19.4.3 on page 242 . rev. 7679h?can?08/08 8-bit microcontroller with 32k/64k/128k bytes of isp flash and can controller at90can32 at90can64 at90can128
2 7679h?can?08/08 at90can32/64/128 1. description 1.1 comparison between at90 can32, at90can64 and at90can128 at90can32, at90can64 and at90can128 are hardware and software compatible. they dif- fer only in memory sizes as shown in table 1-1 . 1.2 part description the at90can32/64/128 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the at90can32/64/128 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consum ption versus processing speed. the avr core combines a rich instruction set with 32 general purpose working registers. all 32 registers are directly connected to the arit hmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. the at90can32/64/128 provides the following fe atures: 32k/64k/128k bytes of in-system pro- grammable flash with read-wh ile-write capabilities, 1k/2k/ 4k bytes eeprom, 2k/4k/4k bytes sram, 53 general purpose i/o lines, 32 general purpose working registers, a can con- troller, real time coun ter (rtc), four flexible timer/coun ters with compare modes and pwm, 2 usarts, a byte oriented two-wire serial interface, an 8-channel 10-bit adc with optional differ- ential input stage with programmable gain, a programmable watchdog timer with internal oscillator, an spi serial port, ie ee std. 1149.1 compliant jtag test interface, also used for accessing the on-chip debug system and programmi ng and five software selectable power sav- ing modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi/can ports and interrupt system to continue f unctioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to main- tain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc, to minimize switching noise during adc conversions. in stan dby mode, the crystal/ resonator oscillator is running while the rest of the device is sleeping. this allows very fast star t-up combined with low power consumption. the device is manufactured using atmel?s high- density nonvolatile memo ry technology. the on- chip isp flash allows the prog ram memory to be reprogrammed in -system through an spi serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the applicatio n flash memory. software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. by table 1-1. memory size summary device flash eeprom ram at90can32 32k bytes 1k byte 2k bytes at90can64 64k bytes 2k bytes 4k bytes at90can128 128k bytes 4k byte 4k bytes 3 7679h?can?08/08 at90can32/64/128 combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel at90can32/64/128 is a powerful microcont roller that provides a highly flexible and cost effective solution to many embedded control applications. the at90can32/64/128 avr is supported with a fu ll suite of program and system development tools including: c compilers, ma cro assemblers, program debugger/simulators, in-circuit emula- tors, and evaluation kits. 1.3 disclaimer typical values contained in th is datasheet are based on simula tions and characterization of other avr microcontrollers manufactured on th e same process technology. min and max values will be available after the device is characterized. 4 7679h?can?08/08 at90can32/64/128 1.4 block diagram figure 1-1. block diagram program counter stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. portb data dir. reg. porte data dir. reg. porta data dir. reg. portd data register portb data register porte data register porta data register portd interrupt unit eeprom spi usart0 status register z y x alu portb drivers porte drivers porta drivers portf drivers portd drivers portc drivers pb7 - pb0 pe7 - pe0 pa7 - pa0 pf7 - pf0 reset vcc agnd gnd aref xtal1 xtal2 control lines + - analog comparator pc7 - pc0 internal oscillator watchdog timer 8-bit data bus avcc usart1 timing and control oscillator oscillator calib. osc data dir. reg. portc data register portc on-chip debug jtag tap programming logic boundary- scan data dir. reg. portf data register portf adc por - bod reset pd7 - pd0 data dir. reg. portg data reg. portg portg drivers pg4 - pg0 two-wire serial interface can controller 5 7679h?can?08/08 at90can32/64/128 1.5 pin configurations figure 1-2. pinout at90can32/64/128 - tqfp pc0 (a8) vcc gnd pf0 (adc0) pf7 (adc7 / tdi) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4 / tck) pf5 (adc5 / tms) pf6 (adc6 / tdo) aref gnd avcc 17 61 60 18 59 20 58 19 21 57 22 56 23 55 24 54 25 53 26 52 27 51 29 28 50 49 32 31 30 (rxd0 / pdi) pe0 (txd0 / pdo) pe1 (xck0 / ain0) pe2 (oc3a / ain1) pe3 (oc3b / int4) pe4 (oc3c / int5) pe5 (t3 / int6) pe6 (icp3 / int7) pe7 (ss) pb0 (sck) pb1 (mosi) pb2 (miso) pb3 (oc2a) pb4 (oc0a / oc1c) pb7 (tosc2 ) pg3 (oc1b) pb6 (tosc1 ) pg4 (oc1a) pb5 pc1 (a9) (t0) pd7 pc2 (a10) pc3 (a11) pc4 (a12) pc5 (a13) pc6 (a14) pc7 (a15 / clko) pa7 (ad7) pg2 (ale) pa6 (ad6) pa5 (ad5) pa4 (ad4) pa3 (ad3) pa0 (ad0) pa1 (ad1) pa2 (ad2) (rxcan / t1) pd6 (txcan / xck1) pd5 (icp1) pd4 (txd1 / int3) pd3 (rxd1 / int2) pd2 (sda / int1) pd1 (scl / int0) pd0 xtal1 xtal2 reset gnd vcc pg1 (rd) pg0 (wr) 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 15 64 63 62 47 46 48 45 44 43 42 41 40 39 38 37 36 35 33 34 (2) (2) nc = do not connect (may be used in future devices) (1) timer2 oscillator (2) nc (1) (64-lead tqfp top view) index corner 6 7679h?can?08/08 at90can32/64/128 figure 1-3. pinout at90can32/64/128 - qfn note: the large center pad underneath the qfn package is made of metal and internally connected to gnd. it should be soldered or glued to the boar d to ensure good mechanical stability. if the center pad is left unconnected, the package might loosen from the board. 1.6 pin descriptions 1.6.1 vcc digital supply voltage. 1.6.2 gnd ground. nc = do not connect (may be used in future devices) (1) timer2 oscillator (2) pc0 (a8) vcc gnd pf0 (adc0) pf7 (adc7 / tdi) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4 / tck) pf5 (adc5 / tms) pf6 (adc6 / tdo) aref gnd avcc (rxd0 / pdi) pe0 (txd0 / pdo) pe1 (xck0 / ain0) pe2 (oc3a / ain1) pe3 (oc3b / int4) pe4 (oc3c / int5) pe5 (t3 / int6) pe6 (icp3 / int7) pe7 (ss) pb0 (sck) pb1 (mosi) pb2 (miso) pb3 (oc2a) pb4 (oc0a / oc1c) pb7 (tosc2 ) pg3 (oc1b) pb6 (tosc1 ) pg4 (oc1a) pb5 pc1 (a9) (t0) pd7 pc2 (a10) pc3 (a11) pc4 (a12) pc5 (a13) pc6 (a14) pc7 (a15 / clko) pa7 (ad7) pg2 (ale) pa6 (ad6) pa5 (ad5) pa4 (ad4) pa3 (ad3) pa0 (ad0) pa1 (ad1) pa2 (ad2) (rxcan / t1) pd6 (txcan / xck1) pd5 (icp1) pd4 (txd1 / int3) pd3 (rxd1 / int2) pd2 (sda / int1) pd1 (scl / int0) pd0 xtal1 xtal2 reset gnd vcc pg1 (rd) pg0 (wr) 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 33 15 47 46 48 45 44 43 42 41 40 39 38 37 36 35 34 (2) (2) nc (1) 17 18 20 19 21 22 23 24 25 26 27 29 28 32 31 30 52 51 50 49 64 63 62 53 61 60 59 58 57 56 55 54 (64-lead qfn top view) index corner 7 7679h?can?08/08 at90can32/64/128 1.6.3 port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pins that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the at90can32/64/128 as listed on page 74 . 1.6.4 port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the at90can32/64/128 as listed on page 76 . 1.6.5 port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port c pins that are exte rnally pulled low will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of special features of the at90can32/64/128 as listed on page 78 . 1.6.6 port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port d pins that are exte rnally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various spec ial features of the at90can32/64/128 as listed on page 80 . 1.6.7 port e (pe7..pe0) port e is an 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pins that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the at90can32/64/128 as listed on page 83 . 1.6.8 port f (pf7..pf0) port f serves as the analog inputs to the a/d converter. 8 7679h?can?08/08 at90can32/64/128 port f also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port f output buffers have sym- metrical drive characteristics with both high sink and source capa bility. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are ac tivated. the port f pins are tri-stated when a reset condition beco mes active, even if the clock is not running. port f also serves the functions of the jtag in terface. if the jtag interface is enabled, the pull- up resistors on pins pf7(tdi), pf5(tms), and pf 4(tck) will be activated even if a reset occurs. 1.6.9 port g (pg4..pg0) port g is a 5-bit i/o port with internal pull-up resistors (selected for eac h bit). the port g output buffers have symmetrical driv e characteristics with both hi gh sink and source capability. as inputs, port g pins that are externally pulled lo w will source current if the pull-up resistors are activated. the port g pins are tr i-stated when a reset condition be comes active, even if the clock is not running. port g also serves the functions of various sp ecial features of the at90can32/64/128 as listed on page 88 . 1.6.10 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset. the minimum pulse length is given in char acteristics. shorter pulses are not guaranteed to generate a reset. th e i/o ports of the avr are immediately reset to their initial state even if the clock is not running. the clock is need ed to reset the rest of the at90can32/64/128. 1.6.11 xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. 1.6.12 xtal2 output from the invert ing oscillator amplifier. 1.6.13 avcc avcc is the supply voltage pin for the a/d converter on port f. it should be externally con- nected to v cc , even if the adc is not used. if the ad c is used, it should be connected to v cc through a low-pass filter. 1.6.14 aref this is the analog reference pin for the a/d converter. 2. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. 9 7679h?can?08/08 at90can32/64/128 3. avr cpu core 3.1 introduction this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access memories, perform calculations, control peri pherals, and handle interrupts. 3.2 architectural overview figure 3-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipe lining. while one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n 10 7679h?can?08/08 at90can32/64/128 the fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle ar ithmetic logic unit (alu ) operation. in a typ- ical alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16 -bit indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic opera- tion, the status register is up dated to reflect information about the result of the operation. program flow is provided by conditional and uncon ditional jump and call instructions, able to directly address the whole addres s space. most avr instructions have a single 16-bit word for- mat. every program memory address co ntains a 16- or 32-bit instruction. program flash memory space is divided in tw o sections, the boot program section and the application program section. both sections have dedicated loc k bits for write and read/write protection. the spm (store program memory) instruction that writes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in th e general data sram, and consequently the stack size is only limited by the total sram size an d the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing mo des supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control r egisters in the i/o spac e with an additional global interrupt enable bit in the status register. all interrupts have a s eparate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector posi- tion. the lower the interr upt vector address, the higher is the priority. the i/o memory space contains 64 addresses for cpu peripheral functi ons as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. in addition, the at90can32/64/128 has extended i/o space from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 3.3 alu ? arithm etic logic unit the high-performance avr alu operates in dire ct connection with all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immedi ate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-functions. some implementations of the architecture also provide a powerful multip lier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set summary? section for a detailed description. 11 7679h?can?08/08 at90can32/64/128 3.4 status register the status register contains information about the result of the most recently executed arith- metic instruction. this information can be used fo r altering program flow in order to perform conditional operations. note that the status re gister is updated after all alu operations, as specified in the instructio n set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically st ored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set to enabled the interrupts. the individual interrupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of t he interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interr upts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the instructio n set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (b it store) use the t-bi t as source or desti- nation for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in so me arithmetic operations. half carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v suppor ts two?s complement arithmetics. see the ?instruction set description? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. bit 76543210 i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 12 7679h?can?08/08 at90can32/64/128 ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruction set description? for de tailed information. 3.5 general purpose register file the register file is optimized for the avr enhanc ed risc instruction set. in order to achieve the required performance and flex ibility, the following in put/output schemes ar e supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input figure 3-2 shows the structure of the 32 genera l purpose working registers in the cpu. figure 3-2. avr cpu general purpose working registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 3-2 , each register is also assigned a data memory address, mapping them directly into the first 32 loca tions of the user data space. although not being physically imple- mented as sram locations, this memory organizati on provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 3.5.1 the x-register, y-register, and z-register the registers r26..r31 have some added functi ons to their general purpose usage. these reg- isters are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 3-3 . 7 0 addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 13 7679h?can?08/08 at90can32/64/128 figure 3-3. the x-, y-, and z-registers in the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (s ee the instruction set reference for details). 3.5.2 extended z-pointer register for elpm/spm ? rampz ? bits 7..1 ? res: reserved bits these bits are reserved for future use and will al ways read as zero. for compatibility with future devices, be sure to write to write them to zero. ? bit 0 ? rampz0: extended ram page z-pointer the rampz register is normally used to sele ct which 64k ram page is accessed by the z- pointer. as the at90can32/64/128 does not support more than 64k of sram memory, this reg- ister is used only to select which page in the program memory is accessed when the elpm/spm instruction is used. the different settings of the rampz0 bit have the following effects: ? at90can32 and at90can64: rampz0 exists as register bit but it is not used for program memory addressing. ? at90can128: rampz0 exists as register bit and it is used for program memory addressing. figure 3-4. the z-pointer used by elpm and spm note: lpm (different of elpm) is never affected by the rampz setting. 15 xh xl 0 x-register 7 0 7 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 7 0 7 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7 0 7 0 r31 (0x1f) r30 (0x1e) bit 76543 2 1 0 ? ? ? ? ? ? ? rampz0 rampz read/write r r r r r r r r/w initial value 0 0 0 0 0 0 0 0 rampz0 = 0: program memory address 0x0000 - 0x7fff (lower 64k bytes) is accessed by elpm/spm rampz0 = 1: program memory address 0x8000 - 0xffff (higher 64k bytes) is accessed by elpm/spm rampz zh zl 7 bit (individually) 0 7 0 7 0 23 bit (z-pointer) 16 15 8 7 0 14 7679h?can?08/08 at90can32/64/128 3.6 stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. the stack pointer register always points to the top of the stack. note that the stack is implemented as growing from higher memory loca- tions to lower memory location s. this implies that a stack push command decreases the stack pointer. the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are located. this stack space in the da ta sram must be defined by the program before any subroutine calls are executed or interrupt s are enabled. the stack pointer must be set to point above 0xff. the stack pointer is decremente d by one when data is pushed onto the stack with the push instruction, and it is decremented by two when the return address is pushed onto the stack with subroutine call or interrupt. the st ack pointer is incremented by one when data is popped from the stack with the pop instruction, and it is incremented by two when data is popped from the stack with return from subr outine ret or return from interrupt reti. the avr stack pointer is implemented as two 8- bit registers in the i/o space. the number of bits actually used is implementation dependent. no te that the data space in some implementa- tions of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present. 3.7 instruction execution timing this section describes the general access timing concepts for instructi on execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clo ck division is used. figure 3-5 shows the parallel instruction fetches and instruction executions enabled by the har- vard architecture and the fast-acc ess register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corr esponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 3-5. the parallel instruction fetche s and instruction executions bit 151413121110 9 8 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00000000 clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu 15 7679h?can?08/08 at90can32/64/128 figure 3-6 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destina- tion register. figure 3-6. single cycle alu operation 3.8 reset and in terrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be writ ten logic one together with the global interrupt enable bit in the status register in orde r to enable the interrupt. depending on the program counter value, interrupts may be automatically disabled when boot lock bits blb02 or blb12 are programmed. this feature improves software security . see the section ?memory program- ming? on page 336 for details. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 60 . the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. the interrupt vectors can be moved to the start of the boot flash section by setting the ivsel bit in the mcu control r egister (mcucr). refer to ?interrupts? on page 60 for more information. the reset vector can also be moved to the start of the boot flash section by programming the bootrst fuse, see ?boot loader support ? read-while-write self-programming? on page 321 . 3.8.1 interrupt behavior when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are dis- abled. the user software can write logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instru ction ? reti ? is executed. there are basically two types of interrupts. the fi rst type is triggered by an event that sets the interrupt flag. for these interrup ts, the program counter is vector ed to the actual interrupt vector in order to execute the interrupt handling rout ine, and hardware clears the corresponding inter- rupt flag. interrupt flags can also be cleared by wr iting a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and re membered until the inte rrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt condit ions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) w ill be set and remembered until the global interrupt enable bit is set, and will th en be executed by order of priority. t otal execution t ime register operands fetch alu operation execute result w rite back t1 t2 t3 t4 clk cpu 16 7679h?can?08/08 at90can32/64/128 the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the in terrupt will not be triggered. when the avr exits from an inte rrupt, it will always retu rn to the main pr ogram and execute one more instruction before any pending interrupt is served. note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the interrup ts will be immediately disabled. no interrupt will be ex ecuted after the cli instru ction, even if it occurs simultaneously with the cli instruction. the following example shows how th is can be used to avoid interrupts during the timed eeprom write sequence. when using the sei instruction to enable interr upts, the instruction following sei will be exe- cuted before any pending interrupts, as shown in this example. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eemwe ; start eeprom write sbi eecr, eewe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 18 7679h?can?08/08 at90can32/64/128 4. memories this section describes the different memories in the at90can32/64/128. the avr architecture has two main memory spaces, the data memory and the program memory space. in addition, the at90can32/64/128 features an eeprom memory for data storage. all three memory spaces are linear and regular. notes: 1. byte address. 2. word (16-bit) address. 4.1 in-system reprogrammabl e flash program memory the at90can32/64/128 contains on-chip in-system reprogrammable flash memory for pro- gram storage (see ?flash size?). since all avr instructions are 16 or 32 bits wide, the flash is organized as 16 bits wide. for software securi ty, the flash program memory space is divided into two sections, boot program section and application program section. the flash memory has an endurance of at least 10,000 write/erase cycles. the at90can32/64/128 program counter (pc) address the program memory locations. the opera- tion of boot program section and associated boot lock bits for so ftware protection are described in detail in ?boot loader support ? read-while-write self-programming? on page 321 . ?memory programming? on page 336 contains a detailed description on flash data serial downloading using the spi pins or the jtag interface. table 4-1. memory mapping. memory mnemonic at90can32 at90can64 at90can128 flash size flash size 32 k bytes 64 k bytes 128 k bytes start address - 0x00000 end address flash end 0x07fff (1) 0x3fff (2) 0x0ffff (1) 0x7fff (2) 0x1ffff (1) 0xffff (2) 32 registers size - 32 bytes start address - 0x0000 end address - 0x001f i/o registers size - 64 bytes start address - 0x0020 end address - 0x005f ext i/o registers size - 160 bytes start address - 0x0060 end address -0x00ff internal sram size isram size 2 k bytes 4 k bytes 4 k bytes start address isram start 0x0100 end address isram end 0x08ff 0x10ff 0x10ff external memory size xmem size 0-64 k bytes start address xmem start 0x0900 0x1100 0x1100 end address xmem end 0xffff eeprom size e2 size 1 k bytes 2 k bytes 4 k bytes start address - 0x0000 end address e2 end 0x03ff 0x07ff 0x0fff 19 7679h?can?08/08 at90can32/64/128 constant tables can be allocated within the entire program memory address space (see the lpm ? load program memory and elpm ? extended load program memory instruction description). timing diagrams for instruction fetc h and execution are presented in ?instruction execution tim- ing? on page 14 . figure 4-1. program memory map 4.2 sram data memory figure 4-2 shows how the at90can32/64/128 sram memory is organized. the at90can32/64/128 is a comp lex microcontroller with more peripheral units than can be supported within the 64 locations reserved in t he opcode for the in and out instructions. for the extended i/o space in sram , only the st/sts/std and ld /lds/ldd instructions can be used. the lower data memory locations address both th e register file, the i /o memory, extended i/o memory, and the internal data sram. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory, and the next locations address the internal data sram (see ?isram size?). an optional external data sram can be used with the at90can32/64/128. this sram will occupy an area in the remaining address locations in the 64k address space. this area starts at the address following the internal sram. the regi ster file, i/o, extended i/o and internal sram occupies the lowest bytes, so when using 64 kb (65,536 bytes) of external memory, ?xmem size? bytes of external memory are available. see ?external memory interface? on page 27 for details on how to take advantage of the external memory map. 0x0000 flash end program memory application flash section boot flash section 20 7679h?can?08/08 at90can32/64/128 4.2.1 sram data access when the addresses accessing the sram memory space exceeds the internal data memory locations, the external data sram is accessed using the same instructions as for the internal data memory access. when the internal data memories are accessed, the read and write strobe pins (pg0 and pg1 ) are inactive during the whole access cycle. external sram operation is enabled by setting the sre bit in the xmcra register. accessing external sram takes one additional clock cycle per byte compared to access of the internal sram. this means that the commands ld, st, lds, sts, ldd, std, push, and pop take one additional clock cycle. if the stack is placed in extern al sram, interrupts, subroutine calls and returns take three clock cycles extra because the two-byte program counter is pushed and popped, and external memory access does not take advantage of the internal pipe-line memory access. when external sram interface is used with wait-state, one-byte external access takes two, three, or four additional cl ock cycles for one, two, and three wait-states respectively. interr upts, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the instruction set manual for one, two, and three wait-states. the five different addressing modes for the data memory cover: direct, indirect with displace- ment, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locations from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i /o registers, 160 extended i/o registers, and the ?isram size? bytes of internal data sr am in the at90can32/64/128 are all accessible through all these addressing modes. the register file is described in ?general purpose regis- ter file? on page 12 . 21 7679h?can?08/08 at90can32/64/128 figure 4-2. data memory map 4.2.2 sram data access times this section describes the general access timi ng concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 4-3 . figure 4-3. on-chip data sram access cycles 32 registers 64 i/o registers internal sram (isram size) 0x0000 - 0x001f 0x0020 - 0x005f xmem start isram end 0xffff 0x0060 - 0x00ff data memory external sram (xmem size) 160 ext i/o reg. isram start clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 22 7679h?can?08/08 at90can32/64/128 4.3 eeprom data memory the at90can32/64/128 contains eeprom memory (see ?e2 siz e?). it is organized as a sepa- rate data space, in which sing le bytes can be read and writ ten. the eeprom has an endurance of at least 100,000 write/ erase cycles. the access betwee n the eeprom and the cpu is described in the following, spec ifying the eeprom address re gisters, the eepr om data reg- ister, and the eeprom control register. for a detailed description of spi, jtag and parallel data downloading to the eeprom, see ?spi serial programming overview? on page 348 , ?jtag programming overview? on page 352 , and ?parallel programming overview? on page 339 respectively. 4.3.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time for the eeprom is given in table 4-2 . a self-timing function, however, lets the user software detect when the next byte can be written. if the user code contains instruc- tions that write the eeprom, some precautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on po wer-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. see ?preventing eeprom co rruption? on page 26. for details on how to avoid problems in these situations. in order to prevent unintentional eeprom writes, a specific write procedure must be followed. refer to the description of the eeprom control regist er for details on this. when the eeprom is read, the cpu is halted for fo ur clock cycles before the next in struction is executed. when the eeprom is written, the cpu is halte d for two clock cycles before the next instruction is executed. 4.3.2 the eeprom address registers ? eearh and eearl ? bits 15..12 ? reserved bits these bits are reserved bits in the at90 can32/64/128 and will a lways read as zero. ? bits 11..0 ? eear11..0: eeprom address the eeprom address registers ? eearh and eearl specify the eeprom address in the eeprom space (see ?e2 size?). the eeprom data bytes are addressed linearly between 0 and ?e2 end?. the initial value of eear is undefined. a proper va lue must be written before the eeprom may be accessed. ? at90can32: eear11 & eear10 exist as re gister bit but they are not used for addressing. ? at90can64: eear11 exists as register bit but it is not used for addressing. bit 15141312 11 10 9 8 ? ? ? ? eear11 eear10 eear9 eear8 eearh eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 7654 3 2 10 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 x x x x xxxx x x xx 23 7679h?can?08/08 at90can32/64/128 4.3.3 the eeprom data register ? eedr ? bits 7..0 ? eedr7.0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address given by the eear regi ster. for the eeprom read operation, the eedr contains the data read out from the eeprom at the add ress given by eear. 4.3.4 the eeprom control register ? eecr ? bits 7..4 ? reserved bits these bits are reserved bits in the at90 can32/64/128 and will a lways read as zero. ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writing eerie to zero disables the interrupt. the eepro m ready interrupt generates a constant inter- rupt when eewe is cleared. ? bit 2 ? eemwe: eeprom master write enable the eemwe bit determines whether setting eewe to one causes the eeprom to be written. when eemwe is set, setting eewe within four cl ock cycles will write data to the eeprom at the selected address if eemwe is zero, sett ing eewe will have no e ffect. when eemwe has been written to one by software, hardware clears th e bit to zero after four clock cycles. see the description of the eewe bit for an eeprom write procedure. ? bit 1 ? eewe: eeprom write enable the eeprom write enable signal eewe is the write strobe to the eeprom. when address and data are correctly set up, the eewe bit must be written to one to write the value into the eeprom. the eemwe bit must be wr itten to one before a logical one is written to eewe, oth- erwise no eeprom write takes place. the follo wing procedure should be followed when writing the eeprom (the order of steps 3 and 4 is not essential): 1. wait until eewe becomes zero. 2. wait until spmen (store program memory enable) in spmcsr (store program mem- ory control and status register) becomes zero. 3. write new eeprom addres s to eear (optional). 4. write new eeprom data to eedr (optional). 5. write a logical one to the eemwe bit while writing a zero to eewe in eecr. 6. within four clock cycles after sett ing eemwe, write a logical one to eewe. the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is co mpleted before initiating a new eeprom write. step 2 is only relevant if the software contai ns a boot loader allowing the cpu to program the flash. if the flash is never being updated by the cpu, step 2 can be omitted. see ?boot loader bit 76543210 eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? ? ? eerie eemwe eewe eere eecr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 x 0 24 7679h?can?08/08 at90can32/64/128 support ? read-while-write self-programming? on page 321 for details about boot programming. caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the eeprom master write enable will time-out. if an interrupt routine accessing the eeprom is interrupting another eeprom acce ss, the eear or eedr register will be modified, causing the interrupted eeprom access to fail. it is recommended to have the global interrupt flag cleared during all the steps to avoid these problems. when the write access time has elapsed, the eewe bit is cleared by hardware. the user soft- ware can poll this bit and wait fo r a zero before writing the next byte. when eewe has been set, the cpu is halted for two cycles before the next instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the re ad strobe to the eeprom. when the correct address is set up in the eear regi ster, the eere bit must be written to a logic one to trigger the eeprom read. the eeprom read access takes one instruction, and the requ ested data is available immediately. when t he eeprom is read, the cpu is ha lted for four cycles before the next instruction is executed. the user should poll the eewe bit before starti ng the read operation. if a write operation is in progress, it is neither possi ble to read the e eprom, nor to change the eear register. the calibrated oscillator is used to time the eeprom accesses. table 4-2 lists the typical pro- gramming time for eeprom access from the cpu. table 4-2. eeprom programming time. symbol number of calibrated rc o scillator cycles typ programming time eeprom write (from cpu) 67 584 8.5 ms 25 7679h?can?08/08 at90can32/64/128 the following code examples show one assembly and one c function for writing to the eeprom. the examples assume that interrupts ar e controlled (e.g. by disabling interrupts glo- bally) so that no interrupts will occur during ex ecution of these functions. the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait for any on going spm command to finish. assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eewe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eemwe sbi eecr,eemwe ; start eeprom write by setting eewe sbi eecr,eewe ret c code example void eeprom_write ( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 28 7679h?can?08/08 at90can32/64/128 figure 4-4. external memory with sector select 4.5.2 using the external memory interface the interface consists of: ? ad7:0: multiplexed low-order address bus and data bus. ? a15:8: high-order address bus (configurable number of bits). ? ale: address latch enable. ?rd : read strobe. ?wr : write strobe. the control bits for the external memory interf ace are located in two registers, the external memory control register a ? xmcra, and the ex ternal memory control register b ? xmcrb. when the xmem interface is enabled, the xmem interface will override th e setting in the data direction registers that corresponds to the ports dedicated to the xmem interface. for details about the port override, see the alternate functions in section ?i/o-ports? on page 66 . the xmem interface will auto-detect whether an access is internal or external. if the access is external, the xmem interface will output address, data, and the control si gnals on the ports according to fig- ure 4-6 (this figure shows the wave forms without wa it-states). when ale goes from high-to-low, there is a valid address on ad7:0. ale is low during a data transfer. when the xmem interface is enabled, also an internal access will caus e activity on address, data and ale ports, but the rd and wr strobes will not toggle duri ng internal access . when the external memory interface is disabled, the normal pin and data direction se ttings are used. note that when the xmem inter- face is disabled, the address space above the internal sram boundary is not mapped into the internal sram. figure 4-5 illustrates how to connect an exte rnal sram to the avr using an octal latch (typically ?74x573? or equivalen t) which is transparent when g is high. 0x0000 isram end external memory (0-64k x 8) 0xffff internal memory srl[2..0] srw11 srw10 srw01 srw00 lower sector upper sector xmem start 29 7679h?can?08/08 at90can32/64/128 4.5.3 address latch requirements due to the high-speed operation of the xram in terface, the address latch must be selected with care for system frequencies above 8 mhz @ 4v and 4 mhz @ 2.7v. when operating at condi- tions above these frequencies, the typical old style 74hc series latch becomes inadequate. the external memory interface is designed in complia nce to the 74ahc series latch. however, most latches can be used as long they comply with the main timing parameters. the main parameters for the address latch are: ? d to q propagation delay (t pd ). ? data setup time before g low (t su ). ? data (address) hold time after g low ( th ). the external memory interface is designed to guaranty minimum address hold time after g is asserted low of t h = 5 ns. refer to t laxx_ld / t llaxx_st in table 26-7 through table 26-14 of sec- tion 26.9 on page 375 . the d-to-q propagation delay (t pd ) must be taken into consideration when calculating the access time requirement of the external componen t. the data setup time before g low (t su ) must not exceed address valid to ale low (t avllc ) minus pcb wiring delay (dependent on the capacitive load). figure 4-5. external sram connected to the avr 4.5.4 pull-up and bus-keeper the pull-ups on the ad7:0 ports may be activated if the corresponding port register is written to one. to reduce power consumpt ion in sleep mode, it is reco mmended to disable the pull-ups by writing the port register to zero before entering sleep. the xmem interface also provides a bus-keeper on the ad7:0 lines. the bus-keeper can be dis- abled and enabled in software as described in ?external memory control register b ? xmcrb? on page 33 . when enabled, the bus-kee per will ensure a defined logic level (zero or one) on the ad7:0 bus when these lines would otherwise be tri-stated by the xmem interface. 4.5.5 timing external memory devices have different timing requirements. to meet these requirements, the at90can32/64/128 xmem interface provides four different wait-states as shown in table 4-4 . it is important to consider the timi ng specification of the external memory device before selecting the wait-state. the most important parameters are the access time for the external memory compared to the set-up requirement of the at90c an32/64/128. the access time for the exter- nal memory is defined to be the time from receivin g the chip select/address until the data of this d[7:0] a[7:0] a[15:8] rd wr sram dq g ad7:0 ale a15:8 rd wr av r 30 7679h?can?08/08 at90can32/64/128 address actually is driven on the bus. the acce ss time cannot exceed the time from the ale pulse must be asserted low until data is stable during a read sequence (see t llrl + t rlrh - t dvrh in table 26-7 through table 26-14 ). the different wait-states are set up in software. as an addi- tional feature, it is possible to divide the ex ternal memory space in two sectors with individual wait-state settings. this makes it possible to connect two different memory devices with different timing requirements to the same xmem interf ace. for xmem interface timing details, please refer to table 26-7 through table 26-14 and figure 26-6 to figure 26-9 in the ?external data memory characteristics? on page 375 . note that the xmem interface is asynchronous and that the waveforms in the following figures are related to the internal system clock. t he skew between the internal and external clock (xtal1) is not guarantied (varies between devices temperature, and supply voltage). conse- quently, the xmem interface is not suited for synchronous operation. figure 4-6. external data memory cycles no wait-state (srwn1=0 and srwn0=0) (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in perio d t4 is only present if the next instruction accesses the ram (internal or external). figure 4-7. external data memory cycles with srwn1 = 0 and srwn0 = 1 (1) ale t1 t2 t3 write read wr t4 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) xxxxx xxxxxxxx ale t1 t2 t3 write read wr t5 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 31 7679h?can?08/08 at90can32/64/128 note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t5 is only present if the next instruction ac cesses the ram (internal or external). figure 4-8. external data memory cycles with srwn1 = 1 and srwn0 = 0 (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t6 is only present if the next instruction ac cesses the ram (internal or external). figure 4-9. external data memory cycles with srwn1 = 1 and srwn0 = 1 (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t7 is only present if the next instruction ac cesses the ram (internal or external). ale t1 t2 t3 write read wr t6 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 t5 ale t1 t2 t3 write read wr t7 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 t5 t6 32 7679h?can?08/08 at90can32/64/128 4.5.6 external memory control register a ? xmcra ? bit 7 ? sre: external sram/xmem enable writing sre to one enables the external memory interface.the pin f unctions ad7:0, a15:8, ale, wr , and rd are activated as the alternate pin functions. the sre bit overrides any pin direction settings in the respective data directio n registers. writ ing sre to zero, disables the external memory interface and the normal pin and data direction settings are used. note that when the xmem interface is disabled, the addr ess space above the internal sram boundary is not mapped into the internal sram. ? bit 6..4 ? srl2, srl1, srl0: wait-state sector limit it is possible to configure di fferent wait-states for different external memory addresses. the external memory address space can be divided in two sectors that have separate wait-state bits. the srl2, srl1, and srl0 bits sele ct the split of the sectors, see table 4-3 and figure 4-4 . by default, the srl2, srl1, and srl0 bits are set to zero and the entire external memory address space is treated as one sector . when the entire sram address sp ace is configured as one sec- tor, the wait-states are configur ed by the srw11 and srw10 bits. note: 1. see table 4-1 on page 18 for ?xmem start? setting. bit 76543210 sre srl2 srl1 srl0 srw11 srw10 srw01 srw00 xmcra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 4-3. sector limits with different settings of srl2..0 srl2 srl1 srl0 sector addressing 000 lower sector n/a upper sector ?xmem start? (1) - 0xffff 001 lower sector ?xmem start? (1) - 0x1fff upper sector 0x2000 - 0xffff 010 lower sector ?xmem start? (1) - 0x3fff upper sector 0x4000 - 0xffff 011 lower sector ?xmem start? (1) - 0x5fff upper sector 0x6000 - 0xffff 100 lower sector ?xmem start? (1) - 0x7fff upper sector 0x8000 - 0xffff 101 lower sector ?xmem start? (1) - 0x9fff upper sector 0xa000 - 0xffff 110 lower sector ?xmem start? (1) - 0xbfff upper sector 0xc000 - 0xffff 111 lower sector ?xmem start? (1) - 0xdfff upper sector 0xe000 - 0xffff 33 7679h?can?08/08 at90can32/64/128 ? bit 3..2 ? srw11, srw10: wait-s tate select bits for upper sector the srw11 and srw10 bits control the number of wait-states for the upper sector of the exter- nal memory address space, see table 4-4 . ? bit 1..0 ? srw01, srw00: wait-state select bits for lower sector the srw01 and srw00 bits control the number of wait-states for the lower sector of the exter- nal memory address space, see table 4-4 . note: 1. n = 0 or 1 (lower/upper sector). for further details of the timing and wait-states of the external memory interface, see figures 4-6 through figures 4-9 for how the setting of the srw bits affects the timing. 4.5.7 external memory control register b ? xmcrb ? bit 7? xmbk: external memory bus-keeper enable writing xmbk to one enables the bus keeper on the ad7:0 lines. when the bus keeper is enabled, it will ensure a defined logic level (zero or one) on ad 7:0 when they would otherwise be tri-stated. writing xmbk to zero disables t he bus keeper. xmbk is not qualified with sre, so even if the xmem interface is disabled, the bus keepers are still activated as long as xmbk is one. ? bit 6..4 ? reserved bits these are reserved bits and will always read as zero. when writing to this address location, write these bits to zero for compatibility with future devices. ? bit 2..0 ? xmm2, xmm1, xmm0: external memory high mask when the external memory is enabled, all port c pins are default used for the high address byte. if the full address space is not required to access the external memory, some , or all, port c pins can be released for normal port pin function as described in table 4-5 . as described in ?using all 64kb locations of external memory? on page 35 , it is possible to use the xmmn bits to access all 64kb locations of the external memory. table 4-4. wait states (1) srwn1 srwn0 wait states 0 0 no wait-states 0 1 wait one cycle during read/write strobe 1 0 wait two cycles during read/write strobe 11 wait two cycles during read/write an d wait one cycle before driving out new address bit 76543210 xmbk ? ? ? ? xmm2 xmm1 xmm0 xmcrb read/write r/w r r r r r/w r/w r/w initial value00000000 34 7679h?can?08/08 at90can32/64/128 4.5.8 using all locations of external memory smaller than 64 kb since the external memory is mapped after the internal memory as shown in figure 4-4 , the external memory is not addressed when addressi ng the first ?isram size? bytes of data space. it may appear that the first ?isram size? bytes of the external memory are inaccessible (external memory addresses 0x0000 to ?isram end?). however, when connecting an external memory smaller than 64 kb, for example 32 kb, these loca tions are easily accessed simply by address- ing from address 0x8000 to ?isram end + 0x8000 ?. since the external memory address bit a15 is not connected to the external memory, addresses 0x8000 to ?isram end + 0x8000? will appear as addresses 0x0000 to ?isram end? for the external memory. addressing above address ?isram end + 0x8000? is not recommended, since this will address an external mem- ory location that is already accessed by another (lower) address. to the application software, the external 32 kb memory will appear as one linear 32 kb address space from ?xmem start? to ?xmem start + 0x8000?. this is illustrated in figure 4-10 . figure 4-10. address map with 32 kb external memory table 4-5. port c pins released as normal port pi ns when the external memory is enabled xmm2 xmm1 xmm0 # bits for external memory address released port pins 0 0 0 8 (full external memory space) none 0017 pc7 0106 pc7 .. pc6 0115 pc7 .. pc5 1004 pc7 .. pc4 1013 pc7 .. pc3 1102 pc7 .. pc2 1 1 1 no address high bits full port c (unused) internal memory 0x0000 xmem start isram end 0xffff avr memory map external memory 0x8000 0x7fff xmem start + 0x8000 isram end + 0x8000 external 32k sram (size=0x8000) 0x7fff 0x0000 xmem start isram end 35 7679h?can?08/08 at90can32/64/128 4.5.9 using all 64kb locations of external memory since the external memory is mapped afte r the internal memory as shown in figure 4-4 , only (64k-(?isram size?+256)) bytes of external memo ry is available by default (address space 0x0000 to ?isram end? is reserved for internal memory). however, it is possible to take advan- tage of the entire external memory by masking th e higher address bits to zero. this can be done by using the xmmn bits and control by software th e most significant bits of the address. by set- ting port c to output 0x00, and releasing the most significant bits for normal port pin operation, the memory interface will addr ess 0x0000 - 0x1fff. see t he following code examples. note: 1. the example code assumes that the part specific header file is included. care must be exercised using this option as most of the memory is masked away. assembly code example (1) ; offset is defined to 0x2000 to ensure ; external memory access ; configure port c (address high byte) to ; output 0x00 when the pins are released ; for normal port pin operation ldi r16, 0xff out ddrc, r16 ldi r16, 0x00 out portc, r16 ; release pc7:5 ldi r16, (1< 37 7679h?can?08/08 at90can32/64/128 5. system clock 5.1 clock systems and their distribution figure 5-1 presents the principal clock systems in the avr and their distribution. all of the clocks need not be active at a given time. in order to reduce power consumptio n, the clocks to unused modules can be halted by using diffe rent sleep modes, as described in ?power management and sleep modes? on page 46 . the clock systems are detailed below. figure 5-1. clock distribution 5.1.1 cpu clock ? clk cpu the cpu clock is routed to parts of the syst em concerned with operat ion of the avr core. examples of such modules are the general pur pose register file, the status register and the data memory holding the stack po inter. halting the cpu clock inhi bits the core from performing general operations and calculations. 5.1.2 i/o clock ? clk i/o the i/o clock is used by the majority of th e i/o modules, like timer/counters, spi, can, usart. the i/o clock is also used by the extern al interrupt module, but note that some external interrupts are detected by asynchronous logic, a llowing such interrupts to be detected even if the i/o clock is halted. also note that address recogn ition in the twi module is carried out asynchro- nously when clk i/o is halted, enabling twi address reception in all sleep modes. 5.1.3 flash clock ? clk flash the flash clock controls operation of the flash interface. the flash clock is usually active simul- taneously with the cpu clock. general i/o modules can controller cpu core ram clk i/o clk asy avr clock control unit clk cpu flash and eeprom clk flash source clock watchdog timer watchdog oscillator reset logic prescaler clock multiplexer multiplexer ckout fuse clko watchdog clock calibrated rc oscillator timer/counter2 oscillator external clock crystal oscillator low-frequency crystal oscillator external clock adc clk adc asynchronous timer/counter2 timer/counter2 tosc2 xtal2 tosc1 xtal1 38 7679h?can?08/08 at90can32/64/128 5.1.4 asynchronous timer clock ? clk asy the asynchronous timer clock al lows the asynchronous timer/c ounter to be clocked directly from an external clock or an external 32 khz clock crystal. the dedicated clock domain allows using this timer/counter as a real-time counter even when the device is in sleep mode. 5.1.5 adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circ uitry. this gives more accurate adc conversion results. 5.2 clock sources the device has the following clock source options, selectable by flash fuse bits as shown below. the clock from the selected source is inpu t to the avr clock generator, and routed to the appropriate modules. note: 1. for all fuses ?1? means unprogrammed while ?0? means programmed. the various choices for each clocking option is given in the following sections. when the cpu wakes up from power-down or power-save, the sele cted clock source is used to time the start- up, ensuring stable osc illator operation bef ore instruction execution st arts. when the cpu starts from reset, there is an additional delay allowing the power to reach a stable level before starting normal operation. the watchdog osc illator is used for ti ming this real-time part of the start-up time. the number of wdt oscillator cycl es used for each time-out is shown in table 5-2 . the frequency of the watchdog oscillator is voltage dependent as shown in ?at90can32/64/128 typical characteristics? on page 384 . 5.3 default clock source the device is shipped with cksel = ?0010?, sut = ?10?, and ckdiv8 programmed. the default clock source setting is the internal rc oscillator with longes t start-up time and an initial system clock prescaling of 8. this default setting ensures that all users can make their desired clock source setting using an in-system or parallel programmer. table 5-1. device clocking options select (1) device clocking option cksel3..0 external crystal/ceramic resonator 1111 - 1000 external low-frequency crystal 0111 - 0100 calibrated internal rc oscillator 0010 external clock 0000 reserved 0011, 0001 table 5-2. number of watchdog oscillator cycles typ time-out (v cc = 5.0v) typ time-out (v cc = 3.0v) number of cycles 4.1 ms 4.3 ms 4k (4,096) 65 ms 69 ms 64k (65,536) 39 7679h?can?08/08 at90can32/64/128 5.4 crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be con- figured for use as an on-chip oscillator, as shown in figure 5-2 . either a quartz crystal or a ceramic resonator may be used. c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the env ironment. some initial guidelines for choosing capacitors for use with crystals are given in table 5-3 . for ceramic resonators, the capacitor values given by the manufacturer should be used. for more info rmation on how to choose capacitors and other details on oscillator operatio n, refer to th e multi-purpose oscilla tor application note. figure 5-2. crystal oscillator connections the oscillator can operate in three different mo des, each optimized for a specific frequency range. the oper ating mode is selected by the fuses cksel3..1 as shown in table 5-3 . note: 1. this option should not be used with crystals, only with ceramic resonators. the cksel0 fuse together with the sut1..0 fuses select the start-up times as shown in table 5-4 . table 5-3. crystal oscillator operating modes cksel3..1 frequency range (mhz) recommended range for capacitors c1 and c2 for use with crystals (pf) 100 (1) 0.4 - 0.9 12 - 22 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 16.0 12 - 22 xtal2 xtal1 gnd c2 c1 40 7679h?can?08/08 at90can32/64/128 notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start- up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with cerami c resonators and will ensure frequency stability at start-up. they can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. 5.5 low-frequency crystal oscillator to use a 32.768 khz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting the cksel fuses to ?010 0?, ?0101?, ?0110?, or ?0111?. the crystal should be connected as shown in figure 5-3 . figure 5-3. low-frequency crystal oscillator connections 12-22 pf capacitors may be necessary if the pa rasitic impedance (pads, wires & pcb) is very low. table 5-4. start-up times for the o scillator clock selection cksel0 sut1..0 start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) recommended usage 0 00 258 ck (1) 14 ck + 4.1 ms ceramic resonator, fast rising power 0 01 258 ck (1) 14 ck + 65 ms ceramic resonator, slowly rising power 010 1k ck (2) 14 ck ceramic resonator, bod enabled 011 1k ck (2) 14 ck + 4.1 ms ceramic resonator, fast rising power 100 1k ck (2) 14 ck + 65 ms ceramic resonator, slowly rising power 1 01 16k ck 14 ck crystal oscillator, bod enabled 1 10 16k ck 14 ck + 4.1 ms crystal oscillator, fast rising power 1 11 16k ck 14 ck + 65 ms crystal oscillator, slowly rising power xtal2 xtal1 gnd 12 - 22 pf 12 - 22 pf 32.768 khz 41 7679h?can?08/08 at90can32/64/128 when this oscillator is selected , start-up times are det ermined by the sut1..0 fuses as shown in table 5-5 and cksel1..0 fuses as shown in table 5-6 . note: 1. these options should only be used if frequency stability at start-up is not important for the application 5.6 calibrated internal rc oscillator the calibrated internal rc oscillator provides a fixed 8.0 mhz clock. the frequency is nominal value at 3v and 25 c. if 8 mhz frequency exceeds the spec ification of the device (depends on v cc ), the ckdiv8 fuse must be programmed in orde r to divide the internal frequency by 8 dur- ing start-up. the device is shipped with the ckdiv8 fuse programmed. see ?system clock prescaler? on page 44. for more details. this clock may be selected as the system clock by pro- gramming the cksel fuses as shown in table 5-7 . if selected, it will operate with no external components. during reset, hardware loads the calibration byte into the osccal register and thereby automatically calibrates the rc oscillator. at 5v and 25 c, this calibration gives a fre- quency within 10% of the nominal frequency. using calibration methods as described in application notes available at www. atmel.com/avr it is possible to achieve 2% accuracy at any given v cc and temperature. when this os cillator is used as the chip clock, the watchdog oscil- lator will still be used for the wa tchdog timer and for th e reset time-out. fo r more information on the pre-programmed calibration value, see the section ?calibration byte? on page 339 . note: 1. the device is shipped with this option selected. table 5-5. start-up times for the lo w-frequency crystal os cillator clock selection sut1..0 additional delay from reset (v cc = 5.0v) recommended usage 00 14 ck fast rising power or bod enabled 01 14 ck + 4.1 ms slowly rising power 10 14 ck + 65 ms stable frequency at start-up 11 reserved table 5-6. start-up times for the lo w-frequency crystal os cillator clock selection cksel3..0 start-up time from power-down and power-save recommended usage 0100 (1) 1k ck 0101 32k ck stable frequency at start-up 0110 (1) 1k ck 0111 32k ck stable frequency at start-up table 5-7. internal calibrated rc o scillator operating modes (1) cksel3..0 nominal frequency 0010 8.0 mhz 42 7679h?can?08/08 at90can32/64/128 when this oscillator is select ed, start-up times are determined by the sut fuses as shown in table 5-8 . note: 1. the device is shipped with this option selected. 5.6.1 oscillator calibra tion register ? osccal ? bit 7 ? reserved bit this bit is reserv ed for future use. ? bits 6..0 ? cal6..0: oscillator calibration value writing the calibration byte to this address will trim the internal oscillator to remove process vari- ations from the oscillator frequency. this is done automatically during chip reset. when osccal is zero, the lowest available frequency is chosen. writing non-zero values to this regis- ter will increase the frequency of the internal oscillator. writing 0x7f to the register gives the highest available freque ncy. the calibrated oscillator is used to time eeprom and flash access. if eeprom or flash is wr itten, do not calibrate to more than 10% above the nominal fre- quency. otherwise, the eeprom or flash write may fail. note that the oscillator is intended for calibration to 8.0 mhz. tuning to other values is not guaranteed, as indicated in table 5-9 . 5.7 external clock to drive the device from an external clock source, xtal1 should be driven as shown in figure 5-4 . to run the device on an ex ternal clock, the cksel fuses must be programme d to ?0000?. table 5-8. start-up times for the internal calib rated rc oscillator clock selection sut1..0 start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck 14 ck bod enabled 01 6 ck 14 ck + 4.1 ms fast rising power 10 (1) 6 ck 14 ck + 65 ms slowly rising power 11 reserved bit 76543210 ? cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 <----- ----------- device specific calibration value ----------- -----> table 5-9. internal rc oscilla tor frequency range. osccal value min frequency in percentage of nominal frequency max frequency in percentage of nominal frequency 0x00 50% 100% 0x3f 75% 150% 0x7f 100% 200% 43 7679h?can?08/08 at90can32/64/128 figure 5-4. external clock drive configuration when this clock source is sele cted, start-up times are determi ned by the sut fuses as shown in table 5-11 . when applying an external clock, it is required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. it is required to en sure that the mcu is kept in reset during such changes in the clock frequency. note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuri ng stable operation. refer to ?system clock prescaler? on page 44 for details. 5.8 clock output buffer when the ckout fuse is prog rammed, the system clock will be ou tput on clko. this mode is suitable when chip clock is used to drive other circuits on the system. the clock will be output also during reset and the normal operation of i/o pin will be over ridden when the fuse is pro- grammed. any clock source, including inter nal rc oscillator, can be selected when clko serves as clock output. if the system clock pres caler is used, it is the divided system clock that is output (ckout fuse programmed). 5.9 timer/counter2 oscillator for avr microcontrollers with timer/counter2 o scillator pins (tosc1 and tosc2), the crystal is connected directly between t he pins. the oscillator is opt imized for use with a 32.768 khz watch crystal. 12-22 pf capacitors may be neces sary if the parasitic impedance (pads, wires & pcb) is very low. table 5-10. external clock frequency cksel3..0 frequency range 0000 0 - 16 mhz table 5-11. start-up times for the external clock selection sut1..0 start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck 14 ck bod enabled 01 6 ck 14 ck + 4.1 ms fast rising power 10 6 ck 14 ck + 65 ms slowly rising power 11 reserved xtal2 xtal1 gnd nc external clock signal 44 7679h?can?08/08 at90can32/64/128 at90can32/64/128 share the timer/counter2 osci llator pins (tosc1 and tosc2) with pg4 and pg3. this means that both pg4 and pg3 can only be used when th e timer/counter2 oscil- lator is not enable. applying an external clock source to tosc1 can be done in asynchronous operation if extclk in the assr register is written to logic one. see ?asynchronous operation of the timer/counter2? on page 160 for further description on selecting external clock as input instead of a 32 khz crystal. in this configuratio n, pg4 cannot be used but pg3 is available. 5.10 system clock prescaler the at90can32/64/128 system clock can be divi ded by setting the clock prescaler register ? clkpr. this feature can be used to decrease power consumption when the requirement for processing power is low. this can be used with al l clock source options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 5-12 . 5.10.1 clock prescaler register ? clkpr ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enable ch ange of the clkps bits. the clkpce bit is only updated when the other bits in cl kpr are simultaneously wr itten to zero. clkpce is cleared by hardware four cycles af ter it is written or when clkps bits are written. rewriting the clkpce bit within this time-out period does neit her extend the time-out period, nor clear the clkpce bit. ? bit 6..0 ? reserved bits these bits are reserv ed for future use. ? bits 3..0 ? clkps3..0: clock prescaler select bits 3 - 0 these bits define the division factor between th e selected clock source and the internal system clock. these bits can be written run-time to va ry the clock frequency to suit the application requirements. as the divider divides the master cl ock input to the mcu, the speed of all synchro- nous peripherals is reduced when a division fact or is used. the division factors are given in table 5-12 . to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write the desired valu e to clkps while writin g a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unprogrammed, the clkps bits will be reset to ?0000?. if ck div8 is programmed, clkps bits are reset to bit 76543210 clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 <----- see bit description -----> 45 7679h?can?08/08 at90can32/64/128 ?0011?, giving a division factor of 8 at start up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. note that any value can be wri tten to the clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequen cy than the maximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. note: the frequency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down source clock. otherwise, interrupts may be lost, and accessing the timer/counter2 regis- ters may fail. table 5-12. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 00001 00012 00104 00118 010016 010132 011064 0111128 1000256 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved 46 7679h?can?08/08 at90can32/64/128 6. power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consump- tion to the application?s requirements. to enter any of the five slee p modes, the se bit in smcr mu st be written to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the smcr register select which sleep mode (idle, adc noise reduction, power-down, power-save, or standby) will be activated by the sleep instruction. see table 6-1 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then ha lted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following sleep. the cont ents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and exe- cutes from the reset vector. figure 5-1 on page 37 presents the different clock systems in the at90 can32/64/128, and their distribution. the figure is helpful in selecting an appropriate sleep mode. 6.0.1 sleep mode control register ? smcr the sleep mode control register contai ns control bits for power management. ? bit 7..4 ? reserved bits these bits are reserv ed for future use. ? bits 3..1 ? sm2..0: sleep mode select bits 2, 1, and 0 these bits select between the five available sleep modes as shown in table 6-1 . note: 1. standby mode is only recommended for use with external crystals or resonators. ? bit 1 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the programmer?s bit 76543210 ? ? ? ? sm2 sm1 sm0 se smcr read/write r r r r r/w r/w r/w r/w initial value00000000 table 6-1. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 010power-down 011power-save 100reserved 101reserved 1 1 0 standby (1) 111reserved 47 7679h?can?08/08 at90can32/64/128 purpose, it is recommended to wr ite the sleep enable (se) bit to one just before the execution of the sleep instruction and to clear it immediately af ter waking up. 6.1 idle mode when the sm2..0 bits are written to 000, t he sleep instruction makes the mcu enter idle mode, stopping the cpu but a llowing spi, can, usart, analog comparator, adc, two-wire serial interface, timer/counters , watchdog, and the interrupt syst em to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow and usart transmit complete interrupts. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator control and status register ? acsr. this will reduce power consumption in idle mode. if t he adc is enabled, a conver sion starts automati- cally when this mode is entered. 6.2 adc noise reduction mode when the sm2..0 bits are written to 001, t he sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but a llowing the adc, the external interrupts, the two-wire serial interface address watch, timer/counter2, can and the watchdog to continue operating (if enabled). this sleep mode basically halts clk i/o , clk cpu , and clk flash , while allowing the other clocks to run. this improves the noise envir onment for the adc, enabling hig her resolution measurements. if the adc is enabled, a conversion starts automatica lly when this mode is entered. apart from the adc conversion complete interrupt, only an external reset, a watchdog reset, a brown-out reset, a two-wire serial interface address match interrupt, a timer/counter2 interrupt, an spm/eeprom ready interrupt, an external level in terrupt on int7:4, or an external interrupt on int3:0 can wake up the mcu from adc noise reduction mode. 6.3 power-down mode when the sm2..0 bits are written to 010, the sleep instruction makes the mcu enter power- down mode. in this mode, the external oscillator is stopped, while the external interrupts, the two-wire serial interface address watch, and the watchdog continue operating (if enabled). only an external reset, a watchdog reset, a brown-out reset, a two-wire serial interface address match interrupt, an exter nal level interrupt on int7:4 , or an external interrupt on int3:0 can wake up the mcu. this sleep mode basically halts all gener ated clocks, allowing operation of asynchronous modules only. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to ?external interrupts? on page 93 for details. when waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effectiv e. this allows the clock to restart and become stable after having been stopped. the wake-up per iod is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 38 . 6.4 power-save mode when the sm2..0 bits are written to 011, the sleep instruction makes the mcu enter power- save mode. this mode is identical to power-down, with one exception: 48 7679h?can?08/08 at90can32/64/128 if timer/counter2 is clocked asyn chronously, i.e., the as2 bit in assr is set, timer/counter2 will run during sleep. the device can wake up from either timer overflow or output compare event from timer/counter2 if the corresponding ti mer/counter2 interrupt enable bits are set in timsk2, and the global interrupt enable bit in sreg is set. if the asynchronous timer is not clocked asynchronously, power-down mode is recommended instead of power-save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in power-save mode if as2 is 0. this sleep mode basically ha lts all clocks except clk asy , allowing operation only of asynchronous modules, including timer/counter2 if clocked asynchronously. 6.5 standby mode when the sm2..0 bits are 110 and an external crystal/resonator cl ock option is selected, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that the oscillator is kept running. fr om standby mode, the device wakes up in 6 clock cycles. notes: 1. only recommended with external crystal or resonator selected as clock source. 2. if as2 bit in assr is set. 3. only int3:0 or level interrupt int7:4. 6.6 minimizing power consumption there are several issues to consider when tryi ng to minimize the power consumption in an avr controlled system. in general, sleep modes shoul d be used as much as possible, and the sleep mode should be selected so that as few as possi ble of the device?s func tions are operating. all functions not needed should be disabled. in parti cular, the following modules may need special consideration when trying to achieve th e lowest possible power consumption. 6.6.1 analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be dis- abled before entering any sleep mode. when th e adc is turned off and on again, the next conversion will be an exte nded conversion. refer to ?analog to digital converter - adc? on page 273 for details on adc operation. table 6-2. active clock domains and wake-up sour ces in the different sleep modes. active clock domains osci llators wake-up sources sleep mode clk cpu clk flash clk io clk adc clk asy main clock source enabled timer osc. enabled int7:0 twi address match timer 2 spm/ eeprom ready adc other i/o idle x x x x x (2) xxxxxx adc noise reduction xx x x (2) x (3) xx (2) xx power- down x (3) x power- save x (2) x (2) x (3) xx (2) standby (1) xx (3) x 49 7679h?can?08/08 at90can32/64/128 6.6.2 analog comparator when entering idle mode, the analog comparator should be disabled if not used. when entering adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comparator is automatically disabled . however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage reference will be enabled, independent of sleep mode. refer to ?analog comparator? on page 269 for details on how to configure the analog comparator. 6.6.3 brown-out detector if the brown-out detector is not needed by the application, this module should be turned off. if the brown-out detector is enabled by the bo dlevel fuses, it will be enabled in all sleep modes, and hence, always consume pow er. in the deeper sl eep modes, this will contribute sig- nificantly to the total current consumption. refer to ?brown-out detect ion? on page 54 for details on how to configure the brown-out detector. 6.6.4 internal voltage reference the internal voltage referenc e will be enabled when needed by the brown-out de tection, the analog comparator or the adc. if these modul es are disabled as described in the sections above, the internal voltage refe rence will be disabled and it w ill not be consuming power. when turned on again, the user must allow the referenc e to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal volt- age reference? on page 56 for details on the start-up time. 6.6.5 watchdog timer if the watchdog timer is not neede d in the application, the module should be turn ed off. if the watchdog timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. in the deeper slee p modes, this will contribute signific antly to the total current consump- tion. refer to ?watchdog timer? on page 57 for details on how to configure the watchdog timer. 6.6.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensures that no power is c onsumed by the input lo gic when not needed. in some cases, the input logic is needed for detec ting wake-up conditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 70 for details on which pins are enabled. if the input buffer is enabl ed and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers (didr1 and didr0). refer to ?digital input disable register 1 ? didr1? on page 272 and ?digital input dis- able register 0 ? didr0? on page 292 for details. 6.6.7 jtag interface and on-chip debug system if the on-chip debug system is enabled by ocden fuse and the chip enter sleep mode, the main clock source is enabled, and hence, alwa ys consumes power. in the deeper sleep modes, 50 7679h?can?08/08 at90can32/64/128 this will contribute significantly to the total curr ent consumption. there ar e three alternative ways to avoid this: ? disable ocden fuse. ? disable jtagen fuse. ? write one to the jtd bit in mcucr. the tdo pin is left floating when the jtag interf ace is enabled while th e jtag tap controller is not shifting data. if the hardware connected to t he tdo pin does not pull up the logic level, power consumption will increase. note that the tdi pin fo r the next device in the scan chain con- tains a pull-up that avoids this problem. writing the jtd bit in the mcucr register to one or leaving the jtag fuse unprogrammed disables the jtag interface. 51 7679h?can?08/08 at90can32/64/128 7. system control and reset 7.1 reset 7.1.1 resetting the avr during reset, all i/o registers are set to their initial values, and the pr ogram starts execution from the reset vector. the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the app lication section while the interrupt vectors are in the boot section or vice versa. the circuit diagram in figure 7-1 shows the reset logic. table 7-1 defines the electrical parameters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the dif- ferent selections for the delay period are presented in ?clock sources? on page 38 . 7.1.2 reset sources the at90can32/64/128 has five sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset when a low level is pr esent on the reset pin for longer than the minimum pulse length. ? watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. ? brown-out reset. the mcu is re set when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. ? jtag avr reset. the mcu is reset as long as th ere is a logic one in the reset register, one of the scan chains of the jtag system. refer to the section ?boundary-scan ieee 1149.1 (jtag)? on page 300 for details. 52 7679h?can?08/08 at90can32/64/128 figure 7-1. reset logic note: 1. the power-on reset will not work unless the supply voltage has been below v pot (falling) 7.1.3 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in table 7-1 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that t he device is properly reset from power-on if v cc started from v por with a rise rate upper than v ccrr . reaching the power-on reset threshold voltage invokes the delay counter, which determine s how long the device is kept in reset after mcu status register (mcusr) brown-out reset circuit bodlevel [2..0] delay counters cksel[3:0] ck timeout wdrf borf extrf porf data bus clock generator spike filter pull-up resistor jtrf jtag reset register watchdog oscillator sut[1:0] power-on reset circuit table 7-1. reset characteristics symbol parameter conditi on min. typ. max. units v pot power-on reset threshold voltage (rising) 1.4 2.3 v power-on reset threshold voltage (falling) (1) 1.3 2.3 v v por vcc start voltage to ensure internal power-on reset signal - 0.05 gnd + 0.05 v v ccrr vcc rise rate to ensure internal power-on reset signal 0.3 v/ms v rst reset pin threshold voltage 0.2 vcc 0.85 vcc v t rst minimum pulse width on reset pin vcc = 5 v, temperature = 25 c 400 ns 53 7679h?can?08/08 at90can32/64/128 v cc rise. the reset signal is activa ted again, without any delay, when v cc decreases below the detection level. figure 7-2. mcu start-up, reset tied to v cc figure 7-3. mcu start-up, reset extended externally note: if v por or v ccrr parameter range can not be followed , an external re set is required. 7.1.4 external reset an external reset is generated by a low level on the reset pin. reset pulses longer than the minimum pulse width (see table 7-1 ) will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. v reset time-out internal reset t tout v pot v por cc v ccrr v ccrr v reset time-out internal reset t tout v rst v por cc v ccrr 54 7679h?can?08/08 at90can32/64/128 figure 7-4. external reset during operation 7.1.5 brown-out detection at90can32/64/128 has an on-chip brown-out dete ction (bod) circuit fo r monitoring the v cc level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by the bodlevel fu ses. the trigger level has a h ysteresis to ensure spike free brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. note: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guar- antees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longe r guaranteed. the test is performed using bodlevel = 010 for low operating voltage and bodlevel = 101 for high operating volt- age . when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 7-5 ), the brown-out reset is i mmediately activated. when v cc increases above the trigger level cc table 7-2. bodlevel fuse coding (1) bodlevel 2..0 fuses min v bot typ v bot max v bot units 111 bod disabled 110 4.1 v 101 4.0 v 100 3.9 v 011 3.8 v 010 2.7 v 001 2.6 v 000 2.5 v table 7-3. brown-out characteristics symbol parameter min. typ. max. units v hyst brown-out detector hysteresis 70 mv t bod min pulse width on brown-out reset 2 s 55 7679h?can?08/08 at90can32/64/128 (v bot+ in figure 7-5 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in vcc if the voltage stays below the trigger level for longer than t bod given in table 7-3 . figure 7-5. brown-out reset during operation 7.1.6 watchdog reset when the watchdog times out, it will generate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay ti mer starts counting the time-out period t tout . refer to page 57 for details on operation of the watchdog timer. figure 7-6. watchdog reset du ring operation v cc reset time-out internal reset v bot- v bot+ t tout ck cc 56 7679h?can?08/08 at90can32/64/128 7.1.7 mcu status register ? mcusr the mcu status register provides information on which reset source caused an mcu reset. ? bit 7..5 ? reserved bits these bits are reserv ed for future use. ? bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caused by a logic one in the jtag reset register selected by the jtag instruction avr_reset. this bit is rese t by a power-on reset, or by writing a logic zero to the flag. ? bit 3 ? wdrf: watchdog reset flag this bit is set if a watchdog re set occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 2 ? borf: brown-out reset flag this bit is set if a brown-out reset occurs. the bi t is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is reset only by writing a logic zero to the flag. to make use of the reset flags to identify a rese t condition, the user should read and then reset the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. 7.2 internal voltage reference at90can32/64/128 features an internal bandgap reference. this reference is used for brown- out detection, and it can be used as an input to the analog comparator or the adc. 7.2.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in table 7-4 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by prog ramming the bodlevel [2..0] fuse). 2. when the bandgap reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, after setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog comparator or bit 76543210 ? ? ? jtrf wdrf borf extrf porf mcusr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 see bit description 57 7679h?can?08/08 at90can32/64/128 adc is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. 7.2.2 voltage reference characteristics 7.3 watchdog timer the watchdog timer is clocked fr om a separate on-chip oscillato r which runs at 1 mhz. this is the typical value at v cc = 5v. see characterization data for typical values at other v cc levels. by controlling the watchdog timer prescaler, the watchdog reset interval can be adjusted as shown in table 7-6 on page 58 . the wdr ? watchdog reset ? instruction resets the watchdog timer. the watchdog timer is also reset when it is disabled and when a chip reset occurs. eight different clock cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the at90can32/64/128 resets and executes from the reset vector. fo r timing details on the watchdog reset, refer to table 7-6 on page 58 . to prevent unintentional disabling of the watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse wdton as shown in table 7-5. refer to ?timed sequences for changing the configur ation of the watchdog timer? on page 59 for details. figure 7-7. watchdog timer table 7-4. internal voltage reference characteristics symbol parameter conditi on min. typ. max. units v bg bandgap reference voltage 1.0 1.1 1.2 v t bg bandgap reference start-up time 40 70 s i bg bandgap reference current consumption 15 a table 7-5. wdt configuration as a function of the fuse settings of wdton wdton safety level wdt initial state how to disable the wdt how to change time-out unprogrammed 1 disabled timed sequence timed sequence programmed 2 enabled always enabled timed sequence watchdog oscillator ~1 mhz 58 7679h?can?08/08 at90can32/64/128 7.3.1 watchdog timer control register ? wdtcr ? bits 7..5 ? reserved bits these bits are reserved bits for future use. ? bit 4 ? wdce: watchdog change enable this bit must be set when the wde bit is writte n to logic zero. otherwis e, the watchdog will not be disabled. once written to one, hardware will clear this bit after four clock cycles. refer to the description of the wde bit for a watchdog disabl e procedure. this bit must also be set when changing the prescaler bits. see ?timed sequences for changing the configuration of the watchdog timer? on page 59. ? bit 3 ? wde: watchdog enable when the wde is written to logic one, the watchdog timer is enabled, and if the wde is written to logic zero, the watchdog timer function is di sabled. wde can only be cleared if the wdce bit has logic level one. to disable an enabled watchdog timer, the following procedure must be followed: 1. in the same operation, write a logic one to wdce and wde. a logic one must be writ- ten to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logic 0 to wde. this disables the watchdog. in safety level 2, it is not possible to disable the watchdog timer, even with the algorithm described above. see ?timed sequences for changing the configuration of the watchdog timer? on page 59. ? bits 2..0 ? wdp2, wdp1, wdp0: watchdog timer prescaler 2, 1, and 0 the wdp2, wdp1, and wdp0 bits determine the watchdog timer prescaling when the watch- dog timer is enabled. the differ ent prescaling values and thei r corresponding timeout periods are shown in table 7-6 . bit 76543210 ? ? ? wdce wde wdp2 wdp1 wdp0 wdtcr read/write r r r r/w r/w r/w r/w r/w initial value00000000 table 7-6. watchdog timer prescale select wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 3.0v typical time-out at v cc = 5.0v 0 0 0 16k cycles 17.1 ms 16.3 ms 0 0 1 32k cycles 34.3 ms 32.5 ms 0 1 0 64k cycles 68.5 ms 65 ms 0 1 1 32/64k cycles 0.14 s 0.13 s 1 0 0 256k cycles 0.27 s 0.26 s 1 0 1 512k cycles 0.55 s 0.52 s 1 1 0 1,024k cycles 1.1 s 1.0 s 1 1 1 2,048k cycles 2.2 s 2.1 s 59 7679h?can?08/08 at90can32/64/128 the following code example shows one assembly and one c function for turning off the wdt. the example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. note: 1. the example code assumes that the part specific header file is included. 7.4 timed sequences for changing the c onfiguration of the watchdog timer the sequence for changing configuration differs slightly between the two safety levels. separate procedures are described for each level. 7.4.1 safety level 1 in this mode, the watchdog time r is initially disabled, but can be enabled by writing the wde bit to 1 without any restriction. a timed sequence is needed when changing the watchdog time-out period or disabling an enabled watchdog time r. to disable an enabled watchdog timer, and/or changing the watchdog time-out, the following procedure must be followed: 1. in the same operation, write a logic one to wdce and wde. a logic one must be writ- ten to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, in the same operation, write the wde and wdp bits as desired, but with the wdce bit cleared. 7.4.2 safety level 2 in this mode, the watchdog time r is always enabled, and the wde bit will always read as one. a timed sequence is needed when changing the watchdog time-out period. to change the watchdog time-out, the following procedure must be followed: 1. in the same operation, write a logical one to wdce and wde. even though the wde always is set, the wde must be written to one to start the timed sequence. 2. within the next four clock cycles, in the sa me operation, write the wdp bits as desired, but with the wdce bit cleared. the value written to the wde bit is irrelevant. assembly code example (1) wdt_off: ; write logical one to wdce and wde ldi r16, (1< 61 7679h?can?08/08 at90can32/64/128 notes: 1. when the ivsel bit in mcucr is set, interru pt vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. 2. when the bootrst fuse is prog rammed, the device will jump to the boot loader address at reset, see ?boot loader support ? read-while-write self-programming? on page 321 . table 8-2 shows reset and interrupt vectors plac ement for the various combinations of bootrst and ivsel settings. if the program never enables an in terrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the applicat ion section while the interrupt vectors are in the boot section or vice versa. note: 1. the boot reset address is shown in table 24-6 on page 334 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup fo r the reset and interrupt vector addresses in at90can32/64/128 is: ;address labels code comments 0x0000 jmp reset ; reset handler 0x0002 jmp ext_int0 ; irq0 handler 0x0004 jmp ext_int1 ; irq1 handler 0x0006 jmp ext_int2 ; irq2 handler 0x0008 jmp ext_int3 ; irq3 handler 0x000a jmp ext_int4 ; irq4 handler 0x000c jmp ext_int5 ; irq5 handler 0x000e jmp ext_int6 ; irq6 handler 0x0010 jmp ext_int7 ; irq7 handler 29 0x0038 timer3 compa timer/counter3 compare match a 30 0x003a timer3 compb timer/counter3 compare match b 31 0x003c timer3 compc timer/counter3 compare match c 32 0x003e timer3 ovf timer/counter3 overflow 33 0x0040 usart1, rx usart1, rx complete 34 0x0042 usart1, udre usart1 data register empty 35 0x0044 usart1, tx usart1, tx complete 36 0x0046 twi two-wire serial interface 37 0x0048 spm ready store program memory ready table 8-2. reset and interrupt vectors placement (1) bootrst ivsel reset address inter rupt vectors start address 1 0 0x0000 0x0002 1 1 0x0000 boot reset address + 0x0002 0 0 boot reset address 0x0002 0 1 boot reset address boot reset address + 0x0002 table 8-1. reset and interrupt vectors (continued) vector no. program address (1) source interrupt definition 62 7679h?can?08/08 at90can32/64/128 0x0012 jmp tim2_comp ; timer2 compare handler 0x0014 jmp tim2_ovf ; timer2 overflow handler 0x0016 jmp tim1_capt ; timer1 capture handler 0x0018 jmp tim1_compa; timer1 comparea handler 0x001a jmp tim1_compb; timer1 compareb handler 0x001c jmp tim1_ovf ; timer1 comparec handler 0x001e jmp tim1_ovf ; timer1 overflow handler 0x0020 jmp tim0_comp ; timer0 compare handler 0x0022 jmp tim0_ovf ; timer0 overflow handler 0x0024 jmp can_it ; can handler 0x0026 jmp ctim_ovf ; can timer overflow handler 0x0028 jmp spi_stc ; spi transfer complete handler 0x002a jmp usart0_rxc; usart0 rx complete handler 0x002c jmp usart0_dre; usart0,udr empty handler 0x002e jmp usart0_txc; usart0 tx complete handler 0x0030 jmp ana_comp ; analog comparator handler 0x0032 jmp adc ; adc conversion complete handler 0x0034 jmp ee_rdy ; eeprom ready handler 0x0036 jmp tim3_capt ; timer3 capture handler 0x0038 jmp tim3_compa; timer3 comparea handler 0x003a jmp tim3_compb; timer3 compareb handler 0x003c jmp tim3_compc; timer3 comparec handler 0x003e jmp tim3_ovf ; timer3 overflow handler 0x0040 jmp usart1_rxc; usart1 rx complete handler 0x0042 jmp usart1_dre; usart1,udr empty handler 0x0044 jmp usart1_txc; usart1 tx complete handler 0x0046 jmp twi ; twi interrupt handler 0x0048 jmp spm_rdy ; spm ready handler ; 0x004a reset: ldi r16, high(ramend) ; main program start 0x004b out sph,r16 ;set stack pointer to top of ram 0x004c ldi r16, low(ramend) 0x004d out spl,r16 0x004e sei ; enable interrupts 0x004f 63 7679h?can?08/08 at90can32/64/128 0x0004 sei ; enable interrupts 0x0005 64 7679h?can?08/08 at90can32/64/128 8.2 moving interrupts between application and boot space the general interrupt control register controls the placement of the interrupt vector table. 8.2.1 mcu control register ? mcucr ? bit 1 ? ivsel: interrupt vector select when the ivsel bit is cleared (z ero), the interrupt vectors are pl aced at the star t of the flash memory. when this bit is set (one), the interrupt vectors are moved to the beginning of the boot loader section of the flash. the actual address of the start of the boot flash section is deter- mined by the bootsz fuses. refer to the section ?boot loader support ? read-while-write self- programming? on page 321 for details. to avoid unintentional ch anges of interrupt vector tables, a special write procedure must be followed to change the ivsel bit: 1. write the interrupt vector change enable (ivce) bit to one. 2. within four cycles, write the desired valu e to ivsel while writ ing a zero to ivce. interrupts will automatically be di sabled while this sequence is executed. interrupts are disabled in the cycle ivce is set, and they remain disabl ed until after the instru ction following the write to ivsel. if ivsel is not written, interrupts remain disabled for four cycles. the i-bit in the status register is unaffected by the automatic disabling. note: if interrupt vectors are placed in the boot loader section and boot lock bit blb02 is pro- grammed, interrupts are disabled while executing fr om the application section. if interrupt vectors are placed in the application section and boot lo ck bit blb12 is programed, interrupts are dis- abled while executing from the boot loader section. refer to the section ?boot loader support ? read-while-write self-programming? on page 321 for details on boot lock bits. bit 76543210 jtd ? ? pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 65 7679h?can?08/08 at90can32/64/128 ? bit 0 ? ivce: interrupt vector change enable the ivce bit must be wr itten to logic one to ena ble change of the ivsel bit. ivce is cleared by hardware four cyc les after it is written or when ivsel is written. sett ing the ivce bit will disable interrupts, as explained in the ivsel description above. see code example below. assembly code example move_interrupts: ; get mcucr in r16, mcucr mov r17, r16 ; enable change of interrupt vectors ori r16, (1< 67 7679h?can?08/08 at90can32/64/128 9.2 ports as general digital i/o the ports are bi-directional i/o port s with optional internal pull-ups. figure 9-2 shows a func- tional description of one i/o-port pin, here generically called pxn. figure 9-2. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. 9.2.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in ?register description for i/o-ports? on page 89 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direct ion of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic ze ro, pxn is configured as an input pin. if portxn is written logic one w hen the pin is configured as an i nput pin, the pull-up resistor is activated. to switch the pull-up re sistor off, portxn has to be wr itten logic zero or the pin has to be configured as an output pin the port pins are tri-stated when reset condition becomes active, even if no clocks are running. clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data bus sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 68 7679h?can?08/08 at90can32/64/128 if portxn is written logic one when the pin is configured as an ou tput pin, the port pin is driven high (one). if portxn is writte n logic zero when the pin is config ured as an output pin, the port pin is driven low (zero). 9.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be us ed to toggle one single bit in a port. 9.2.3 switching between input and output when switching between tri-state ({ddxn, port xn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) occu rs. normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the di fference between a strong high driver and a pull-up. if this is not the case, the pud bit in th e mcucr register can be set to disable all pull- ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 9-1 summarizes the control signals for the pin value. 9.2.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bi t. as shown in figure 9-2 , the pinxn register bit and the preceding latch con- stitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 9-3 shows a timing dia- gram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 9-1. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no default configuration after reset. tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 69 7679h?can?08/08 at90can32/64/128 figure 9-3. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system cl ock. the latch is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indi- cated by the two arrows t pd,max and t pd,min , a single signal transiti on on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in figure 9-4 . the out instruction sets the ?sy nc latch? signal at the positive edge of the clock. in this case, the delay t pd through the synchronizer is 1 system clock period. figure 9-4. synchronization when reading a software assigned pin value xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 70 7679h?can?08/08 at90can32/64/128 the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups as signed to port pins 6 and 7. the resulting pin values are read back again, but as previously di scussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. note: 1. for the assembly program, two temporary re gisters are used to minimize the time from pull- ups are set on pins 0, 1, 6, and 7, until the di rection bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 9.2.5 digital input enable and sleep modes as shown in figure 9-2 , the digital input signal can be clamped to ground at the input of the schmitt-trigger. the signal denot ed sleep in the figure, is set by the mcu sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as ex ternal interrupt pins. if the external interrupt request is not e nabled, sleep is active also for these pi ns. sleep is also over ridden by various other alternate functions as described in ?alternate port functions? on page 71 . if a logic high level (?one?) is present on an asynchronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16, (1< 72 7679h?can?08/08 at90can32/64/128 figure 9-5. alternate port functions (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. all other signals are unique for each pin. table 9-2 summarizes the function of the overri ding signals. the pin and port indexes from figure 9-5 are not shown in the succeeding tables. the overriding signals are generated internally in the modules having the alternate function. clk rpx rrx wrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q set clr 0 1 0 1 0 1 dixn aioxn dieoexn pvovxn pvoexn ddovxn ddoexn puoexn puovxn puoexn: pxn pull-up override enable puovxn: pxn pull-up override value ddoexn: pxn data direction override enable ddovxn: pxn data direction override value pvoexn: pxn port value override enable pvovxn: pxn port value override value dixn: digital input pin n on portx aioxn: analog input/output pin n on portx reset reset q q d clr q q d clr q q d clr pinxn portxn ddxn data bus 0 1 dieovxn sleep dieoexn: pxn digital input-enable override enable dieovxn: pxn digital input-enable override value sleep: sleep control pxn i/o 0 1 ptoexn wpx ptoexn: pxn, port toggle override enable wpx: write pinx 73 7679h?can?08/08 at90can32/64/128 the following subsections shortly describe the alte rnate functions for each port, and relate the overriding signals to the alternate function. refer to the alternate function description for further details. 9.3.1 mcu control register ? mcucr table 9-2. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the outp ut driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital i nput is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to /from alternate functions. the signal is connected directly to the pad, and can be used bi- directionally. bit 7 6 5 4 3 2 1 0 jtd ? ?pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 74 7679h?can?08/08 at90can32/64/128 ? bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable t he pull-ups ({ddxn, portxn} = 0b01). see ?con- figuring the pin? for more details about this feature. 9.3.2 alternate functions of port a the port a has an alternate function as the address low byte and data lines for the external memory interface. the port a pins with altern ate functions are shown in table 9-3 . the alternate pin configuration is as follows: ? ad7 ? port a, bit 7 ad7, external memory interface address 7 and data 7. ? ad6 ? port a, bit 6 ad6, external memory interface address 6 and data 6. ? ad5 ? port a, bit 5 ad5, external memory interface address 5 and data 5. ? ad4 ? port a, bit 4 ad4, external memory interface address 4 and data 4. ? ad3 ? port a, bit 3 ad3, external memory interface address 3 and data 3. ? ad2 ? port a, bit 2 ad2, external memory interface address 2 and data 2. ? ad1 ? port a, bit 1 ad1, external memory interface address 1 and data 1. ? ad0 ? port a, bit 0 ad0, external memory interface address 0 and data 0. table 9-3. port a pins alternate functions port pin alternate function pa7 ad7 (external memory interface address and data bit 7) pa6 ad6 (external memory interface address and data bit 6) pa5 ad5 (external memory interface address and data bit 5) pa4 ad4 (external memory interface address and data bit 4) pa3 ad3 (external memory interface address and data bit 3) pa2 ad2 (external memory interface address and data bit 2) pa1 ad1 (external memory interface address and data bit 1) pa0 ad0 (external memory interface address and data bit 0) 75 7679h?can?08/08 at90can32/64/128 table 9-4 and table 9-5 relates the alternate functions of po rt a to the overriding signals shown in figure 9-5 on page 72 . note: 1. ada is short for address active and represents the time when address is output. see ?exter- nal memory interface? on page 27 for details. note: 1. ada is short for address active and represents the time when address is output. see ?exter- nal memory interface? on page 27 for details. table 9-4. overriding signals for alternate functions in pa7..pa4 signal name pa7/ad7 pa6/ad6 pa5/ad5 pa4/ad4 puoe sre ? (ada (1) + wr ) sre ? (ada (1) + wr ) sre ? (ada (1) + wr ) sre ? (ada (1) + wr ) puov0000 ddoe sre sre sre sre ddov wr + ada wr + ada wr + ada wr + ada pvoe sre sre sre sre pvov a7 ? ada (1) + d7 output ? wr a6 ? ada (1) + d6 output ? wr a5 ? ada (1) + d5 output ? wr a4 ? ada (1) + d4 output ? wr ptoe0000 dieoe0000 dieov0000 di d7 input d6 input d5 input d4 input aio???? table 9-5. overriding signals for alternate functions in pa3..pa0 signal name pa3/ad3 p a2/ad2 pa1/ad1 pa0/ad0 puoe sre ? (ada (1) + wr ) sre ? (ada (1) + wr ) sre ? (ada (1) + wr ) sre ? (ada (1) + wr ) puov0000 ddoe sre sre sre sre ddov wr + ada wr + ada wr + ada wr + ada pvoe sre sre sre sre pvov a3 ? ada (1) + d3 output ? wr a2 ? ada (1) + d2 output ? wr a1 ? ada (1) + d1 output ? wr a0 ? ada (1) + d0 output ? wr ptoe0000 dieoe0000 dieov0000 di d3 input d2 input d1 input d0 input aio???? 76 7679h?can?08/08 at90can32/64/128 9.3.3 alternate functions of port b the port b pins with altern ate functions are shown in table 9-6 . the alternate pin configuration is as follows: ?oc0a/oc1c, bit 7 oc0a, output compare match a output. the pb7 pi n can serve as an external output for the timer/counter0 output compare a. the pin has to be configured as an output (ddb7 set ?one?) to serve this function. the oc0a pin is also the output pin for the pwm mode timer function. oc1c, output compare match c output. the pb7 pi n can serve as an external output for the timer/counter1 output compare c. the pin has to be configured as an output (ddb7 set ?one?) to serve this function. the oc1c pin is also the output pin for the pwm mode timer function. ? oc1b, bit 6 oc1b, output compare match b output. the pb6 pi n can serve as an external output for the timer/counter1 output compare b. the pin has to be configured as an output (ddb6 set ?one?) to serve this function. the oc1b pin is also the output pin for the pwm mode timer function. ? oc1a, bit 5 oc1a, output compare match a output. the pb5 pi n can serve as an external output for the timer/counter1 output compare a. the pin has to be configured as an output (ddb5 set ?one?) to serve this function. the oc1a pin is also the output pin for the pwm mode timer function. ? oc2a, bit 4 oc2a, output compare match a output. the pb4 pi n can serve as an external output for the timer/counter2 output compare a. the pin has to be configured as an output (ddb4 set ?one?) to serve this function. the oc2a pin is also the output pin for the pwm mode timer function. ? miso ? port b, bit 3 miso, master data input, slave data output pi n for spi channel. when the spi is enabled as a master, this pin is configured as an input r egardless of the setting of ddb3. when the spi is enabled as a slave, the data direction of this pi n is controlled by ddb3. when the pin is forced to be an input, the pull- up can still be controlled by the portb3 bit. ? mosi ? port b, bit 2 table 9-6. port b pins alternate functions port pin alternate functions pb7 oc0a/oc1c (output compare and pwm output a for timer/counter0 or output compare and pwm output c fo r timer/counter1) pb6 oc1b (output compare and pwm output b for timer/counter1) pb5 oc1a (output compare and pwm output a for timer/counter1) pb4 oc2a (output compare and pwm output a for timer/counter2 ) pb3 miso (spi bus master input/slave output) pb2 mosi (spi bus master output/slave input) pb1 sck (spi bus serial clock) pb0 ss (spi slave select input) 77 7679h?can?08/08 at90can32/64/128 mosi, spi master data output, sl ave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input regar dless of the setting of ddb2. when the spi is enabled as a master, the data dire ction of this pin is controlled by ddb2. when the pin is forced to be an input, the pull-up can st ill be controlled by the portb2 bit. ? sck ? port b, bit 1 sck, master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input regar dless of the setting of ddb1. when the spi is enabled as a master, the data dire ction of this pin is controlled by ddb1. when the pin is forced to be an input, the pull-up can st ill be controlled by the portb1 bit. ?ss ? port b, bit 0 ss , slave port select input. when the spi is enab led as a slave, this pi n is configured as an input regardless of the setting of ddb0. as a slav e, the spi is activated when this pin is driven low. when the spi is enabled as a master, the data di rection of this pin is controlled by ddb0. when the pin is forced to be an input, the pull-up can still be controlled by the portb0 bit. table 9-7 and table 9-8 relate the alternate functions of po rt b to the overri ding signals shown in figure 9-5 on page 72 . spi mstr input and spi slave output constitute the miso sig- nal, while mosi is divided into spi mstr output and spi slave input. table 9-7 and table 9-8 relates the alternate functions of po rt b to the overriding signals shown in figure 9-5 on page 72 . note: 1. see ?output compare modula tor - ocm? on page 165 for details. table 9-7. overriding signals for alternate functions in pb7..pb4 signal name pb7/oc0a/oc1c pb6/oc1b pb5/oc1a pb4/oc2a puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe oc0a/oc1c enable (1) oc1b enable oc1a enable oc2a enable pvov oc0a/oc1c (1) oc1b oc1a oc2a ptoe 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di ? ? ? ? aio ? ? ? ? 78 7679h?can?08/08 at90can32/64/128 9.3.4 alternate functions of port c the port c has an alternate function as the address high byte for the external memory interface. the port c pins with alternate functions are shown in table 9-9 . the alternate pin configuration is as follows: ? a15/clko ? port c, bit 7 a15, external memory interface address 15. clko, divided system clock: the divided syst em clock can be output on the pc7 pin. the divided system clock will be output if the ck out fuse is programmed, regardless of the portc7 and ddc7 settings. it w ill also be output during reset. table 9-8. overriding signals for alternate functions in pb3..pb0 signal name pb3/miso pb 2/mosi pb1/sck pb0/ss puoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr puov portb3 ? pud portb2 ? pud portb1 ? pud portb0 ? pud ddoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr ddov0000 pvoe spe ? mstr spe ? mstr spe ? mstr 0 pvov spi slave output spi master output sck output 0 ptoe0000 dieoe0000 dieov0000 di spi master input spi slave input ? reset sck input spi ss aio???? table 9-9. port c pins alternate functions port pin alter nate function pc7 a15/clko (external memory interf ace address 15 or divided system clock) pc6 a14 (external memory interface address 14) pc5 a13 (external memory interface address 13) pc4 a12 (external memory interface address 12) pc3 a11 (external memory interface address 11) pc2 a10 (external memory interface address 10) pc1 a9 (external memory interface address 9) pc0 a8 (external memory interface address 8) 79 7679h?can?08/08 at90can32/64/128 ? a14 ? port c, bit 6 a14, external memory interface address 14. ? a13 ? port c, bit 5 a13, external memory interface address 13. ? a12 ? port c, bit 4 a12, external memory interface address 12. ? a11 ? port c, bit 3 a11, external memory interface address 11. ? a10 ? port c, bit 2 a10, external memory interface address 10. ? a9 ? port c, bit 1 a9, external memory interface address 9. ? a8 ? port c, bit 0 a8, external memory interface address 8. table 9-10 and table 9-11 relate the alternate functions of port c to the overriding signals shown in figure 9-5 on page 72 . note: 1. ckout is one if the ckout fuse is programmed table 9-10. overriding signals for alternate functions in pc7..pc4 signal name pc7/a15 pc6/a14 pc5/a13 pc4/a12 puoe sre ? (xmm < 1) sre ? (xmm < 2) sre ? (xmm < 3) sre ? (xmm < 4) puov 0 0 0 0 ddoe ckout (1) + (sre ? (xmm < 1)) sre ? (xmm < 2) sre ? (xmm < 3) sre ? (xmm < 4) ddov 1 1 1 1 pvoe ckout (1) + (sre ? (xmm < 1)) sre ? (xmm < 2) sre ? (xmm < 3) sre ? (xmm < 4) pvov (a15 ? ckout (1) ) + (clko ? ckout (1) ) a14 a13 a12 ptoe 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di ? ? ? ? aio ? ? ? ? 80 7679h?can?08/08 at90can32/64/128 9.3.5 alternate functions of port d the port d pins with alternate functions are shown in table 9-12 . the alternate pin configuration is as follows: ? t0 ? port d, bit 7 t0, timer/counter0 counter source. ? rxcan/t1 ? port d, bit 6 rxcan, can receive data (data input pin for the can). when the can controller is enabled this pin is configured as an input regardless of the value of ddd6. when the can forces this pin to be an input, the pull-up can st ill be controlled by the portd6 bit. t1, timer/counter1 counter source. ? txcan/xck1 ? port d, bit 5 table 9-11. overriding signals for alternate functions in pc3..pc0 signal name pc3/a11 p c2/a10 pc1/a9 pc0/a8 puoe sre ? (xmm < 5) sre ? (xmm < 6) sre ? (xmm < 7) sre ? (xmm < 7) puov0000 ddoe sre ? (xmm < 5) sre ? (xmm < 6) sre ? (xmm < 7) sre ? (xmm < 7) ddov1111 pvoe sre ? (xmm < 5) sre ? (xmm < 6) sre ? (xmm < 7) sre ? (xmm < 7) pvov a11 a10 a9 a8 ptoe0000 dieoe0000 dieov0000 di???? aio???? table 9-12. port d pins alternate functions port pin alternate function pd7 t0 (timer/counter0 clock input) pd6 rxcan/t1 (can receive pin or timer/counter1 clock input) pd5 txcan/xck1 (can transmit pin or usart1 external clock input/output) pd4 icp1 (timer/counter1 input capture trigger) pd3 int3/txd1 (external interrupt 3 input or uart1 transmit pin) pd2 int2/rxd1 (external interrupt2 input or uart1 receive pin) pd1 int1/sda (external interrupt 1 input or twi serial data) pd0 int0/scl (external interrupt0 input or twi serial clock) 81 7679h?can?08/08 at90can32/64/128 txcan, can transmit data (data output pin for the can). when the can is enabled, this pin is configured as an output regardless of the value of ddd5. xck1, usart1 external clock. th e data direction register (ddd5) controls whether the clock is output (ddd5 set) or input (ddd45 clear ed). the xck1 pin is active only when the usart1 operates in synchronous mode. ? icp1 ? port d, bit 4 icp1, input capture pin1. the pd4 pin can act as an input capture pin for timer/counter1. ? int3/txd1 ? port d, bit 3 int3, external interrupt source 3. the pd3 pin c an serve as an external interrupt source to the mcu. txd1, transmit data (data output pin for t he usart1). when the usart1 transmitter is enabled, this pin is configured as an output regardless of the value of ddd3. ? int2/rxd1 ? port d, bit 2 int2, external interrupt source 2. the pd2 pin can serve as an external interrupt source to the mcu. rxd1, receive data (data input pin for the u sart1). when the usart1 receiver is enabled this pin is configured as an input regardless of the value of ddd2. when the usart forces this pin to be an input, the pull-up can still be controlled by the portd2 bit. ? int1/sda ? port d, bit 1 int1, external interrupt source 1. the pd1 pin c an serve as an external interrupt source to the mcu. sda, two-wire serial interface data. when the twen bit in twcr is set (one) to enable the two-wire serial interface, pin pd1 is disconnected from the port and becomes the serial data i/o pin for the two-wire serial inte rface. in this mode, there is a spike filter on the pin to sup- press spikes shorter than 50 ns on the input signal , and the pin is driven by an open drain driver with slew-rate limitation. ? int0/scl ? port d, bit 0 int0, external interrupt source 0. the pd0 pin c an serve as an external interrupt source to the mcu. scl, two-wire serial interface clock: when the twen bit in twcr is set (one) to enable the two-wire serial interface, pin pd0 is disconnec ted from the port and bec omes the serial clock i/o pin for the two-wire serial inte rface. in this mode, there is a spike filter on the pin to sup- press spikes shorter than 50 ns on the input signal , and the pin is driven by an open drain driver with slew-rate limitation. 82 7679h?can?08/08 at90can32/64/128 table 9-13 and table 9-14 relates the alternate functions of port d to the overriding signals shown in figure 9-5 on page 72 . note: 1. when enabled, the two-wire serial interface enables slew-rate controls on the output pins pd0 and pd1. this is not shown in this table. in addition, spike filters are connected between the aio outputs shown in the port figure and the digital logic of the twi module. table 9-13. overriding signals for alternate functions pd7..pd4 signal name pd7/t0 pd6/t1/r xcan pd5/xck1/txcan pd4/icp1 puoe 0 rxcanen txcanen + 0 puov 0 portd6 ? pud 00 ddoe 0 rxcanen txcanen 0 ddov 0 0 1 0 pvoe 0 0 txcanen + umsel1 0 pvov 0 0 (xck1 output ? umsel1 ? txcanen ) + (txcan ? txcanen) 0 ptoe 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di t0 input t1 input/rxcan xck1 input icp1 input aio ? ? ? ? table 9-14. overriding signals for alternate functions in pd3..pd0 (1) signal name pd3/int3/t xd1 pd2/int2/rxd1 pd1/int1/sda pd0/int0/scl puoe txen1 rxen1 twen twen puov 0 portd2 ? pud portd1 ? pud portd0 ? pud ddoe txen1 rxen1 0 0 ddov 1 0 0 0 pvoe txen1 0 twen twen pvov txd1 0 sda_out scl_out ptoe 0 0 0 0 dieoe int3 enable int2 enabl e int1 enable int0 enable dieov int3 enable int2 enabl e int1 enable int0 enable di int3 input int2 input/rx d1 int1 input int0 input aio ? ? sda input scl input 83 7679h?can?08/08 at90can32/64/128 9.3.6 alternate functions of port e the port e pins with altern ate functions are shown in table 9-15 . the alternate pin configuration is as follows: ? pcint7/icp3 ? port e, bit 7 int7, external interrup t source 7. the pe7 pin can serve as an external interrupt source. icp3, input capture pin3: the pe7 pin can act as an input capture pin for timer/counter3. ? int6/t3 ? port e, bit 6 int6, external interrup t source 6. the pe6 pin can serve as an external interrupt source. t3, timer/counter3 counter source. ? int5/oc3c ? port e, bit 5 int5, external interrup t source 5. the pe5 pin can serve as an external interrupt source. oc3c, output compare match c output. the pe5 pin can serve as an external output for the timer/counter3 output compare c. the pin has to be configured as an output (dde5 set ?one?) to serve this function. the oc3c pin is also the output pin for the pwm mode timer function. ? int4/oc3b ? port e, bit 4 int4, external interrup t source 4. the pe4 pin can serve as an external interrupt source. oc3b, output compare match b output. the pe4 pin can serve as an external output for the timer/counter3 output compare b. the pin has to be configured as an output (dde4 set (one)) to serve this function. the oc3b pin is also the output pin for the pwm mode timer function. ? ain1/oc3a ? port e, bit 3 ain1 ? analog comparator negative input. this pi n is directly connected to the negative input of the analog comparator. oc3a, output compare match a output. the pe3 pin can serve as an external output for the timer/counter3 output compare a. the pin has to be configured as an output (dde3 set ?one?) to serve this function. the oc3a pin is also the output pin for the pwm mode timer function. table 9-15. port e pins alternate functions port pin alternate function pe7 int7/icp3 (external interrupt 7 input or timer/counter3 input capture trigger) pe6 int6/ t3 (external interrupt 6 input or timer/counter3 clock input) pe5 int5/oc3c (external interrupt 5 input or output compare and pwm output c for timer/counter3) pe4 int4/oc3b (external interrupt4 input or output compare and pwm output b for timer/counter3) pe3 ain1/oc3a (analog comparator negative in put or output compare and pwm output a for timer/counter3) pe2 ain0/xck0 (analog comparator positive i nput or usart0 external clock input/output) pe1 pdo/txd0 (programming data output or uart0 transmit pin) pe0 pdi/rxd0 (programming data input or uart0 receive pin) 84 7679h?can?08/08 at90can32/64/128 ? ain0/xck0 ? port e, bit 2 ain0 ? analog comparator positive input. this pin is directly connected to the positive input of the analog comparator. xck0, usart0 external cl ock. the data direction register (dde2) controls whether the clock is output (dde2 set) or input (dde2 cleared) . the xck0 pin is active only when the usart0 operates in synchronous mode. ? pdo/txd0 ? port e, bit 1 pdo, spi serial programming data output. duri ng serial program downloading, this pin is used as data output line for the at90can32/64/128. txd0, uart0 transmit pin. ? pdi/rxd0 ? port e, bit 0 pdi, spi serial programming data input. during serial program downloading, this pin is used as data input line for the at90can32/64/128. rxd0, usart0 receive pin. receive data (data input pin for the usart0). when the usart0 receiver is enabled this pin is configured as an input regardless of the value of ddre0. when the usart0 forces this pi n to be an input, a logical one in porte0 will turn on the inter- nal pull-up. table 9-16 and table 9-17 relates the alternate functions of port e to the overriding signals shown in figure 9-5 on page 72 . table 9-16. overriding signals for alternate functions pe7..pe4 signal name pe7/int7/icp3 pe6/in t6/t3 pe5/int5/oc 3c pe4/int4/oc3b puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 0 oc3c enable oc3b enable pvov 0 0 oc3c oc3b ptoe 0 0 0 0 dieoe int7 enable int6 enable int5 enable int4 enable dieov int7 enable int6 enable int5 enable int4 enable di int7 input /icp3 input int6 input /t3 input int5 input int4 input aio ? ? ? ? 85 7679h?can?08/08 at90can32/64/128 note: 1. ain0d and ain1d is described in ?digital input disable register 1 ? didr1? on page 272 . 9.3.7 alternate functions of port f the port f has an alternate function as analog input for the adc as shown in table 9-18 . if some port f pins are configured as outputs, it is essential that these do not switch when a con- version is in progress. this might corrupt the re sult of the conversion. if the jtag interface is enabled, the pull-up resistors on pins pf7 (tdi ), pf5 (tms) and pf4 (tck) will be activated even if a reset occurs. the alternate pin configuration is as follows: ? tdi, adc7 ? port f, bit 7 adc7, analog to digital converter, input channel 7 . table 9-17. overriding signals for alternate functions in pe3..pe0 signal name pe3/ain1/o c3a pe2/ain0/xck0 pe1/p do/txd0 pe0/pdi/rxd0 puoe 0 0 txen0 rxen0 puov000porte0 ? pud ddoe 0 0 txen0 rxen0 ddov0010 pvoe oc3a enable umsel0 txen0 0 pvov oc3a xck0 output txd0 0 ptoe0000 dieoe ain1d (1) ain0d (1) 00 dieov0000 di 0 xck0 input ? rxd0 aio ain1 input ain0 input ? ? table 9-18. port f pins alternate functions port pin alternate function pf7 adc7/tdi (adc input channel 7 or jtag data input) pf6 adc6/tdo (adc input channel 6 or jtag data output) pf5 adc5/tms (adc input channel 5 or jtag mode select) pf4 adc4/tck (adc input channel 4 or jtag clock) pf3 adc3 (adc input channel 3) pf2 adc2 (adc input channel 2) pf1 adc1 (adc input channel 1) pf0 adc0 (adc input channel 0) 86 7679h?can?08/08 at90can32/64/128 tdi, jtag test data in. serial input data to be sh ifted in to the instruction register or data reg- ister (scan chains). when the jtag interface is enabled, this pin can not be used as an i/o pin. ? tck, adc6 ? port f, bit 6 adc6, analog to digital converter, input channel 6 . tdo, jtag test data out. serial output data fr om instruction register or data register. when the jtag interface is enabled, this pin can not be used as an i/o pin. ? tms, adc5 ? port f, bit 5 adc5, analog to digital converter, input channel 5 . tms, jtag test mode select. this pin is used for navigating through the tap-controller state machine. when the jtag interface is enabled, this pin can not be used as an i/o pin. ? tdo, adc4 ? port f, bit 4 adc4, analog to digital converter, input channel 4 . tck, jtag test clock. jtag operation is synchronous to tck. when the jtag interface is enabled, this pin can not be used as an i/o pin. ? adc3 ? port f, bit 3 adc3, analog to digital converter, input channel 3. ? adc2 ? port f, bit 2 adc2, analog to digital converter, input channel 2. ? adc1 ? port f, bit 1 adc1, analog to digital converter, input channel 1. ? adc0 ? port f, bit 0 adc0, analog to digital converter, input channel 0. 87 7679h?can?08/08 at90can32/64/128 table 9-19 and table 9-20 relates the alternate functions of port f to the overriding signals shown in figure 9-5 on page 72 . table 9-19. overriding signals for alternate functions in pf7..pf4 signal name pf 7/adc7/tdi pf6/adc6/tdo pf5/adc5/tms pf4/adc4/tck puoe jtagen jtagen jtagen jtagen puov jtagen jtagen jtagen jtagen ddoe jtagen jtagen jtagen jtagen ddov 0 shift_ir + shift_dr 00 pvoe jtagen jtagen jtagen jtagen pvov 0 tdo 0 0 ptoe0000 dieoe jtagen + adc7d jtagen + adc6d jtagen + adc5d jtagen + adc4d dieov jtagen 0 jtagen jtagen di tdi ? tms tck aio adc7 input adc6 input adc5 input adc4 input table 9-20. overriding signals for alternate functions in pf3..pf0 signal name pf3/adc3 pf 2/adc2 pf1/adc1 pf0/adc0 puoe0000 puov0000 ddoe0000 ddov0000 pvoe0000 pvov0000 ptoe0000 dieoe adc3d adc2d adc1d adc0d dieov0000 di???? aio adc3 input adc2 input adc1 input adc0 input 88 7679h?can?08/08 at90can32/64/128 9.3.8 alternate functions of port g the alternate pin configuration is as follows: the alternate pin configuration is as follows: ? tosc1 ? port g, bit 4 tosc2, timer/counter2 os cillator pin 1. when the as2 bit in assr is set (one) to enable asyn- chronous clocking of timer/counter2, pin pg 4 is disconnected from t he port, and becomes the input of the inverting oscillator am plifier. in this mode , a crystal oscillator is connected to this pin, and the pin can not be used as an i/o pin. ? tosc2 ? port g, bit 3 tosc2, timer/counter2 os cillator pin 2. when the as2 bit in assr is set (one) to enable asyn- chronous clocking of timer/counter2, pin pg 3 is disconnected from t he port, and becomes the inverting output of the oscillator am plifier. in this mode, a crystal oscillator is co nnected to this pin, and the pin can not be used as an i/o pin. ?ale ? port g, bit 2 ale is the external data memory address latch enable signal. ?rd ? port g, bit 1 rd is the external data me mory read control strobe. ?wr ? port g, bit 0 wr is the external data me mory write control strobe. table 9-21. port g pins alternate functions port pin alternate function pg4 tosc1 (rtc oscillator timer/counter2) pg3 tosc2 (rtc oscillator timer/counter2) pg2 ale (address latch enable to external memory) pg1 rd (read strobe to external memory) pg0 wr (write strobe to external memory) 89 7679h?can?08/08 at90can32/64/128 table 9-21 and table 9-22 relates the alternate functions of port g to the overriding signals shown in figure 9-5 on page 72 . 9.4 register description for i/o-ports 9.4.1 port a data register ? porta table 9-22. overriding signals for alternate function in pg4 signal name---pg4/tosc1 puoe as2 puov 0 ddoe as2 ddov 0 pvoe 0 pvov 0 ptoe 0 dieoe as2 dieov exclk di ? aio t/c2 osc input table 9-23. overriding signals for alte rnate functions in pg3:0 signal name pg3/tosc 2 pg2/ale pg1/rd pg0/wr puoe as2 ? exclk sre sre sre puov0 000 ddoe as2 ? exclk sre sre sre ddov 0 1 1 1 pvoe 0 sre sre sre pvov 0 ale rd wr ptoe0 000 dieoe as2 0 0 0 dieov0 000 di? ??? aio t/c2 osc output ? ? ? bit 76543210 porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 90 7679h?can?08/08 at90can32/64/128 9.4.2 port a data direction register ? ddra 9.4.3 port a input pins address ? pina 9.4.4 port b data register ? portb 9.4.5 port b data direction register ? ddrb 9.4.6 port b input pins address ? pinb 9.4.7 port c data register ? portc 9.4.8 port c data direction register ? ddrc 9.4.9 port c input pins address ? pinc bit 76543210 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pina7 pina6 pina5 pina4 pi na3 pina2 pina1 pina0 pina read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portb7 portb6 portb5 portb4 port b3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pinb7 pinb6 pinb5 pinb4 pi nb3 pinb2 pinb1 pinb0 pinb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portc7 portc6 portc5 portc4 port c3 portc2 portc1 portc0 portc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pinc7 pinc6 pinc5 pinc4 pi nc3 pinc2 pinc1 pinc0 pinc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a 91 7679h?can?08/08 at90can32/64/128 9.4.10 port d data register ? portd 9.4.11 port d data di rection register ? ddrd 9.4.12 port d input pins address ? pind 9.4.13 port e data register ? porte 9.4.14 port e data direction register ? ddre 9.4.15 port e input pins address ? pine 9.4.16 port f data register ? portf 9.4.17 port f data direction register ? ddrf bit 76543210 portd7 portd6 portd5 portd4 port d3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pind7 pind6 pind5 pind4 pi nd3 pind2 pind1 pind0 pind read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 porte read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 ddre read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 pine read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portf7 portf6 portf5 portf4 port f3 portf2 portf1 portf0 portf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 ddrf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 92 7679h?can?08/08 at90can32/64/128 9.4.18 port f input pins address ? pinf 9.4.19 port g data register ? portg 9.4.20 port g data direction register ? ddrg 9.4.21 port g input pins address ? ping bit 76543210 pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 pinf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 ? ? ? portg4 portg3 portg2 portg1 portg0 portg read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ? ? ? ddg4 ddg3 ddg2 ddg1 ddg0 ddrg read/write r r r r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? ? ping4 ping3 ping2 ping1 ping0 ping read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 n/a n/a n/a n/a n/a 93 7679h?can?08/08 at90can32/64/128 10. external interrupts the external interrupts are triggered by the int7:0 pins. observe that, if enabled, the interrupts will trigger even if th e int7:0 pins are configur ed as outputs. this feat ure provides a way of gen- erating a software interrupt. the ex ternal interrupts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the specification for the exter nal interrupt control reg- isters ? eicra (int3:0) and eicrb (int7:4) . when the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. note that recognition of falling or rising edge interrupts on int7:4 requires the presence of an i/o clock, described in ?clock systems and their distribution? on page 37 . low level interrupts and the edge interrupt on int3:0 are detected asynchronously. this implies that these interrupts can be used for waking the part also from sleep modes other than idle mode. the i/o clock is halted in all sleep modes except idle mode. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some ti me to wake up the mcu. this makes the mcu less sensitive to noise. the changed level is sampled twice by the watchdog oscillator clock. the period of the watchdog oscillator is 1 s (nominal) at 5.0v and 25 c. the frequency of the watchdog oscilla- tor is voltage dependent as shown in the ?electrical characteristics (1)? on page 365 . the mcu will wake up if the input has the requ ired level during this sampling or if it is held until the end of the start-up time. the start-up time is de fined by the sut fuses as described in ?system clock? on page 37 . if the level is sampled twice by the watc hdog oscillator clock bu t disappea rs before the end of the start-up time, the mcu will still wake up, but no interrupt will be generated. the required level must be held long enough for the mcu to complete the wake up to trigger the level interrupt. 10.1 external interrupt register description 10.1.1 asynchronous external interrupt control register a ? eicra ? bits 7..0 ? isc31, isc30 ? isc01, isc00: asynchronous external interrupt 3 - 0 sense control bits the external interrupts 3 - 0 are activated by the external pins int3:0 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the level and edges on the external pins that activate the interrupts are defined in table 10-1 . edges on int3..int0 are registered asynchro- nously. pulses on int3:0 pins wider than the minimum pulse width given in table 10-2 will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. if enabled, a level triggered interrupt will generate an inter- rupt request as long as the pin is held low. wh en changing the iscn bit, an interrupt can occur. therefore, it is recommended to first disable intn by clearing its interrupt enable bit in the eimsk register. then, the iscn bit can be changed. finally, the intn interrupt flag should be cleared by writing a logical one to its interrupt flag bit (intfn) in the eifr register before the interrupt is re-enabled. bit 76543210 isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 eicra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 94 7679h?can?08/08 at90can32/64/128 note: 1. n = 3, 2, 1 or 0. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. 10.1.2 synchronous external interrupt control register b ? eicrb ? bits 7..0 ? isc71, isc70 - isc41, isc40: synchronous external interrupt 7 - 4 sense control bits the external interrupts 7 - 4 are activated by the external pins int7:4 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the level and edges on the external pins that activate the interrupts are defined in table 10-3 . the value on the int7:4 pins are sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an inter- rupt. observe that cpu clock frequency can be lower than the xtal frequency if the xtal divider is enabled. if low level interrupt is select ed, the low level must be held until the comple- tion of the currently ex ecuting instruction to generate an interrupt. if enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. note: 1. n = 7, 6, 5 or 4. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. table 10-1. asynchronous external interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of intn generates an interrupt request. 0 1 any logical change on intn generates an interrupt request 1 0 the falling edge of intn generates asynchronously an interrupt request. 1 1 the rising edge of intn generates asynchronously an interrupt request. table 10-2. asynchronous external interrupt characteristics symbol parameter condition min typ max units t int minimum pulse width for asynchronous external interrupt 50 ns bit 76543210 isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 eicrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 10-3. synchronous external interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of intn generates an interrupt request. 0 1 any logical change on intn generates an interrupt request 1 0 the falling edge between two samples of intn generates an interrupt request. 1 1 the rising edge between two samples of intn generates an interrupt request. 95 7679h?can?08/08 at90can32/64/128 10.1.3 external interrupt mask register ? eimsk ? bits 7..0 ? int7 ? int0: external interrupt request 7 - 0 enable when an int7 ? int0 bit is written to one and t he i-bit in the status register (sreg) is set (one), the corresponding external pin interrupt is enabled. the interrupt sense control bits in the external interrupt control registers ? eicra an d eicrb ? defines whethe r the external inter- rupt is activated on risi ng or falling edge or level sensed. acti vity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. this provides a way of generating a software interrupt. 10.1.4 external interrupt flag register ? eifr ? bits 7..0 ? intf7 - intf0: external interrupt flags 7 - 0 when an edge or logic change on the int7:0 pin triggers an interrupt request, intf7:0 becomes set (one). if the i-bit in sreg and the corresp onding interrupt enable bit, int7:0 in eimsk, are set (one), the mcu will jump to the interrupt vector . the flag is cleared wh en the interr upt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. these flags are always cleared when int7:0 are configured as level interrupt. note that when entering sleep mode with the int3:0 interrupts disabled, the input buffers on these pins will be disabled. this may cause a logic change in internal si gnals which will set the intf3:0 flags. see ?digital input enable and sleep modes? on page 70 for more information. bit 76543210 int7 int6 int5 int4 int3 int2 int1 iint0 eimsk read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 intf7 intf6 intf5 intf4 intf3 intf2 intf1 iintf0 eifr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 96 7679h?can?08/08 at90can32/64/128 11. timer/counter3/1/0 prescalers timer/counter3, timer/counter1 and timer/counte r0 share the same prescaler module, but the timer/counters can have differ ent prescaler settings. the des cription below applies to both timer/counter3, timer/counter1 and timer/counter0. 11.1 overview most bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number. 11.1.1 internal clock source the timer/counter can be clocked directly by th e system clock (by setting the csn2:0 = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 11.1.2 prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/counter, and it is shared by timer/counter3, timer/coun ter1 and timer/counter0. since the prescaler is not affected by the timer/counte r?s clock select, the state of the prescaler will have implications for situations where a prescal ed clock is used. one exam ple of prescaling arti- facts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycl es from when the timer is enable d to the first count occurs can be from 1 to n+1 system clock cycles, where n equa ls the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizing the timer/counter to program execu- tion. however, care must be taken if the othe r timer/counter that shares the same prescaler also uses prescaling. a prescaler reset will affect the prescaler period for all timer/counters it is connected to. 11.1.3 external clock source an external clock source applied to the t3/t1/t0 pin can be used as timer/counter clock (clk t3 /clk t1 /clk t0 ). the t3/t1/t0 pin is sampled once ev ery system clock cycle by the pin syn- chronization logic. the synchronized (sampled) si gnal is then passed through the edge detector. figure 11-1 shows a functional equival ent block diagram of the t3/t1/t0 synchronization and edge detector logic. the registers are clocked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t3 /clk t1 /clk t0 pulse for each positive (csn2:0 = 7) or nega- tive (csn2:0 = 6) edge it detects. 97 7679h?can?08/08 at90can32/64/128 figure 11-1. t3/t1/t0 pin sampling the synchronization and e dge detector logic introduces a de lay of 2.5 to 3.5 system clock cycles from an edge has been applied to the t3/t1/t0 pin to the counter is updated. enabling and disabling of the clock input mu st be done when t3/t1/t0 has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. each half period of the exter nal clock applied must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the sys- tem clock frequency (f extclk 99 7679h?can?08/08 at90can32/64/128 12. 8-bit timer/counter0 with pwm timer/counter0 is a general purpose, single channel, 8-bit timer/counter module. the main features are: 12.1 features ? single channel counter ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (pwm) ? frequency generator ? external event counter ? 10-bit clock prescaler ? overflow and compare match interrupt sources (tov0 and ocf0a) 12.2 overview many register and bit references in this section are written in general form. ? a lower case ?n? replaces the timer/counter number, in this case 0. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 c ounter value and so on. ? a lower case ?x? replaces the output compare unit channel, in this case a. however, when using the register or bit defines in a program, the precise form must be used, i.e., ocr0a for accessing timer/counter0 output compare channel a value and so on. a simplified block diagram of the 8-bit timer/counter is shown in figure 12-1 . for the actual placement of i/o pins, refer to ?pin configurations? on page 5 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit loca- tions are listed in the ?8-bit timer/counter register description? on page 109 . figure 12-1. 8-bit timer/counter block diagram timer/counter data bus = tcntn waveform generation ocnx = 0 control logic = 0xff bottom count clear direction tovn (int.req.) ocrnx tccrn clock select tn edge detector ( from prescaler ) clk tn top ocn (int.req.) 100 7679h?can?08/08 at90can32/64/128 12.2.1 registers the timer/counter (tcnt0) and output compare register (ocr0a) are 8-bit registers. inter- rupt request (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifr0). all interrupts are indivi dually masked with the timer interrupt mask reg- ister (timsk0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via th e prescaler, or by an external clock source on the t0 pin. the clock select logic block contro ls which clock source and edge the timer/counter uses to increment (or decrement) its value. th e timer/counter is inactive when no clock source is selected. the output from th e clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare register (ocr0a) is compared with the timer/counter value at all times. the result of the compare can be used by the waveform generator to gener- ate a pwm or variable frequency output on the output compare pin (oc0a). see ?output compare unit? on page 101. for details. the compare match event will also set the compare flag (ocf0a) which can be used to generate an output compare interrupt request. 12.2.2 definitions the following definitions are used ex tensively throughout the section: 12.3 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs02:0) bits located in the timer/counter control register (tccr0a). for details on clock sources and pres- caler, see ?timer/counter3/1/0 prescalers? on page 96 . 12.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 12-2 shows a block diagram of the counter and its surroundings. figure 12-2. counter unit block diagram bottom the counter reaches the bottom when it becomes 0x00. max the counter reaches its maximum wh en it becomes 0xff (decimal 255). top the counter reaches the to p when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment is depen- dent on the mode of operation. data bus tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn bottom direction clear 101 7679h?can?08/08 at90can32/64/128 signal description (internal signals): count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set all bits to zero). clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. bottom signalize that tcnt0 has re ached minimum value (zero). depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source, selected by the clock select bits (cs02:0). w hen no clock source is selected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the se tting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare output oc0a. for more details about advanced count ing sequences and waveform generation, see ?modes of operation? on page 104 . the timer/counter overflow flag (tov0) is set a ccording to the mode of operation selected by the wgm01:0 bits. tov0 can be us ed for generating a cpu interrupt. 12.5 output compare unit the 8-bit comparator continuously compares tcnt0 with the output compare register (ocr0a). whenever tcnt0 equals ocr0a, the com parator signals a match. a match will set the output compare flag (ocf0a) at the next timer clock cycle. if enabled (ocie0a = 1 and global interrupt flag in sreg is set), the ou tput compare flag genera tes an output compare interrupt. the ocf0a flag is automatically cleare d when the interrupt is executed. alternatively, the ocf0a flag can be cleared by software by wr iting a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the wgm01:0 bits and compare output mode (com0a1:0) bits. the max and bottom sig- nals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( see ?modes of operation? on page 104. ). 102 7679h?can?08/08 at90can32/64/128 figure 12-3 shows a block diagram of the output compare unit. figure 12-3. output compare unit, block diagram the ocr0a register is double buffered when us ing any of the pulse wi dth modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buff- ering is disabled. the double buffering synchronizes the update of the ocr0a compare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr0a register access may seem complex, but this is not case. when the double buffer- ing is enabled, the cpu has access to the ocr0 a buffer register, and if double buffering is disabled the cpu will access the ocr0a directly. 12.5.1 force output compare in non-pwm waveform generation modes, the matc h output of the comparator can be forced by writing a one to the fo rce output compare (foc0a) bit. fo rcing compare match will not set the ocf0a flag or reload/clear the ti mer, but the oc0a pin will be updated as if a real compare match had occurred (the com0a1:0 bits settings define whether the oc0a pin is set, cleared or toggled). 12.5.2 compare match blocking by tcnt0 write all cpu write operations to th e tcnt0 register will block any co mpare match that occur in the next timer clock cycle, even when the timer is stopped. this feature allo ws ocr0a to be initial- ized to the same value as tcnt0 without trigge ring an interrupt when the timer/counter clock is enabled. 12.5.3 using the output compare unit since writing tcnt0 in any mode of operation will block all comp are matches for one timer clock cycle, there are risks involved when changing tcnt0 when using the output compare channel, independently of whether the time r/counter is running or not. if the value written to tcnt0 equals the ocr0a value, the compare match will be missed, resulting in incorrect waveform ocfnx (int.req.) = (8-bit comparator ) ocrnx ocnx data bus tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 103 7679h?can?08/08 at90can32/64/128 generation. similarly, do not write the tcnt0 value equal to bottom when the counter is downcounting. the setup of the oc0a should be performed befo re setting the data direc tion register for the port pin to output. the easiest way of setting the oc0a value is to use the force output com- pare (foc0a) strobe bits in normal mode. the oc0a register keeps its value even when changing between waveform generation modes. be aware that the com0a1:0 bits are not double buffered together with the compare value. changing the com0a1:0 bits will take effect immediately. 12.6 compare match output unit the compare output mode (com0a1:0) bits have two functions. the waveform generator uses the com0a1:0 bits for defining the output compare (oc0a) state at the next compare match. also, the com0a1:0 bits control the oc0a pin output source. figure 12-4 shows a sim- plified schematic of the logic affected by the com0a1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control regis- ters (ddr and port) that are affected by the co m0a1:0 bits are shown. when referring to the oc0a state, the reference is for the internal oc 0a register, not the oc0a pin. if a system reset occur, the oc0a register is reset to ?0?. figure 12-4. compare match output unit, schematic 12.6.1 compare output function the general i/o port function is overridden by the output compare (oc0a) from the waveform generator if either of the com0a1:0 bits are se t. however, the oc0a pin direction (input or out- put) is still controlled by the da ta direction register (ddr) for th e port pin. the data direction register bit for the oc0a pin (ddr_oc0a) must be set as output before the oc0a value is vis- ible on the pin. the port override function is independent of the waveform generation mode. the design of the output compare pin logic allo ws initialization of the oc0a state before the output is enabled. note that some com0a1:0 bit settings are reserved for certain modes of operation. see ?8-bit timer/counter register description? on page 109. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data bus focnx clk i/o 104 7679h?can?08/08 at90can32/64/128 12.6.2 compare output mode and waveform generation the waveform generator uses the com0a1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com0a1:0 = 0 tells the waveform generator that no action on the oc0a register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 12-2 on page 110 . for fast pwm mode, refer to table 12- 3 on page 110 , and for phase correct pwm refer to table 12-4 on page 111 . a change of the com0a1:0 bits st ate will have effect at the first compare match after the bits are written. for non-pwm modes, the action can be fo rced to have immediate effect by using the foc0a strobe bits. 12.7 modes of operation the mode of operation, i.e., t he behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm01:0) and compare output mode (com0a1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. th e com0a1:0 bits control whether the pwm output generated should be inverted or not (i nverted or non-inverted pwm). for non-pwm modes the com0a1:0 bits control whether the output should be set, cleared, or toggled at a compare match ( see ?compare match output unit? on page 103. ). for detailed timing information refer to figure 12-8 , figure 12-9 , figure 12-10 and figure 12-11 in ?timer/counter timing diagrams? on page 108 . 12.7.1 normal mode the simplest mode of operation is the normal mode (wgm01:0 = 0). in this mode the counting direction is always up (incre menting), and no counter clear is performed. the counter simply overruns when it passes its maxi mum 8-bit value (top = 0xff) and then restarts from the bot- tom (0x00). in normal o peration the timer/counter overflow flag (tov0) will be set in the same timer clock cycle as the tcnt0 becomes zero. the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. ho wever, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 12.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm 01:0 = 2), the ocr0a register is used to manipulate the counter resolution . in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0a. the ocr0a de fines the top value fo r the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 12-5 . the counter value (tcnt0) increases until a compare match occurs between tcnt0 and o cr0a, and then counter (tcnt0) is cleared. 105 7679h?can?08/08 at90can32/64/128 figure 12-5. ctc mode, timing diagram an interrupt can be generated each time the c ounter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the inte rrupt handler routine can be used for updating the top value. however, changing top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value wri tten to ocr0a is lower than the current value of tcnt0, the counter will miss the co mpare match. the counter will then have to count to its max- imum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, t he oc0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will not be visible on the port pin unless the data direction for the pin is set to output. the wavefo rm generated will have a maximum frequency of f oc0a = f clk_i/o /2 when ocr0a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov0 flag is set in the same time r clock cycle that the counter counts fr om max to 0x00. 12.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm01:0 = 3) provides a high frequency pwm waveform generation option. the fast pwm di ffers from the other pwm option by its sin- gle-slope operation. the counter counts from bottom to max then restarts from bottom. in non-inverting compare output mode, the output compare (oc0a) is cleared on the compare match between tcnt0 and ocr0a, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac app lications. high frequency a llows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the max value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 12-6 . the tcnt0 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. the diagram includes non-inverted and tcntn ocnx (toggle) ocnx interrupt flag set 1 4 period 2 3 (comnx1:0 = 1) f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = 106 7679h?can?08/08 at90can32/64/128 inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0a and tcnt0. figure 12-6. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reac hes max. if the inter- rupt is enabled, the interrupt handler routi ne can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc0a pin. setting the com0a1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com0a1:0 to three (see table 12-3 on page 110 ). the actual oc0a value will only be visible on the port pin if the data direction for the port pin is set as out- put. the pwm waveform is generated by setting (or clearing) the oc0a register at the compare match between ocr0a and tcnt0, and clearing (or setting) the oc0a register at the timer clock cycle the counter is cleared (changes from max to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represents special cases when generating a pwm waveform output in the fast pwm mode. if t he ocr0a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr0a equal to max will result in a constantly high or low output (depending on the polarity of the out put set by the com0a1:0 bits.) a frequency (with 50% duty cycle) waveform out put in fast pwm mode can be achieved by set- ting oc0a to toggle its logical level on each compare match (com0a1:0 = 1). the waveform generated will have a maximum frequency of f oc0a = f clk_i/o /2 when ocr0a is set to zero. this feature is similar to the oc0a toggle in ctc mo de, except the double buff er feature of the out- put compare unit is enabled in the fast pwm mode. tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 f ocnxpwm f clk_i/o n 256 ? ------------------ = 107 7679h?can?08/08 at90can32/64/128 12.7.4 phase correct pwm mode the phase correct pwm mode (wgm01:0 = 1) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to max and then from m ax to bottom. in non- inverting compare output mode, the output comp are (oc0a) is cleared on the compare match between tcnt0 and ocr0a while upcounting, and set on the compare match while down- counting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the sym- metric feature of the dual-slope pwm modes, t hese modes are preferred for motor control applications. the pwm resolution for the phase correct pwm m ode is fixed to eight bits. in phase correct pwm mode the counter is incremented until the counter value matches m ax. when the counter reaches max, it changes the count direction. the tcnt0 value will be equal to max for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 12-7 . the tcnt0 value is in the timing diagram shown as a histogram for illu strating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0a and tcnt0. figure 12-7. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc0a pin. setti ng the com0a1:0 bits to two will pr oduce a non-inverted pwm. an inverted pwm output can be generated by setting the com0a1:0 to three (see table 12-4 on page 111 ). the actual oc0a value will only be visible on the port pi n if the data direction for the port pin is set as output. the pwm waveform is generated by clearing (or setting) the oc0a register at the compare match between ocr0a and tcnt0 when the counter increments, and setting (or clearing) the oc0a register at compare match between ocr0a and tcnt0 when the counter tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update 108 7679h?can?08/08 at90can32/64/128 decrements. the pwm frequency for the output when using phase correct pwm can be calcu- lated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represent special cases when generating a pwm waveform output in the phase correct pwm mo de. if the ocr0a is set equal to bottom, the output will be continuously low an d if set equal to max the output will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. 12.8 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 12-8 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 12-8. timer/counter timing diagram, no prescaling figure 12-9 shows the same timing data, but with the prescaler enabled. figure 12-9. timer/counter timing diagram, with prescaler (f clk_i/o /8) f ocnxpcpwm f clk_i/o n 510 ? ------------------ = clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) 109 7679h?can?08/08 at90can32/64/128 figure 12-10 shows the setting of ocf0a in all modes except ctc mode. figure 12-10. timer/counter timing diagram, setting of ocf0a, with prescaler (f clk_i/o /8) figure 12-11 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode. figure 12-11. timer/counter timing diagram, clear timer on compare match mode, with pres- caler (f clk_i/o /8) 12.9 8-bit timer/counter register description 12.9.1 timer/counter0 cont rol register a ? tccr0a ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm00 bit specifies a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0a is written when operating in pwm mode. when writing a logical one to the foc0a bit, an immediate com- pare match is forced on the waveform generati on unit. the oc0a output is changed according to its com0a1:0 bits setting. note that the foc0 a bit is implemented as a strobe. therefore it is the value present in the com0a1:0 bits that determines the effect of the forced compare. a foc0a strobe will not gen erate any interrupt, nor will it cl ear the timer in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 7 6 5 4 3 2 1 0 foc0a wgm00 com0a1 com0a0 wgm01 cs02 cs01 cs00 tccr0a read/write w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 110 7679h?can?08/08 at90can32/64/128 ? bit 6, 3 ? wgm01:0: waveform generation mode these bits control the counting sequence of th e counter, the source for the maximum (top) counter value, and what type of waveform gener ation to be used. mode s of operation supported by the timer/counter unit are: normal mode, clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes. see table 12-1 and ?modes of operation? on page 104 . note: 1. the ctc0 and pwm0 bit definition names are now obsolete. use the wgm01:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. ? bit 5:4 ? com01:0: compare match output mode these bits control the output compare pin (oc0a) behavior. if one or both of the com0a1:0 bits are set, the oc0a output overrides the normal po rt functionality of the i/o pin it is connected to. however, note that the data direction r egister (ddr) bit corresponding to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the function of the com0a1:0 bits depends on the wgm01:0 bit setting. table 12-2 shows the com0a1:0 bit func tionality when the wgm01:0 bits are set to a normal or ctc mode (non-pwm). table 12-3 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to fast pwm mode. table 12-1. waveform generation mode bit description (1) mode wgm01 (ctc0) wgm00 (pwm0) timer/counter mode of operation top update of ocr0a at tov0 flag set on 0 0 0 normal 0xff immediate max 1 0 1 pwm, phase correct 0xff top bottom 2 1 0 ctc ocr0a immediate max 3 1 1 fast pwm 0xff top max table 12-2. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 12-3. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01reserved 10 clear oc0a on compare match. set oc0a at top 11 set oc0a on compare match. clear oc0a at top 111 7679h?can?08/08 at90can32/64/128 note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the se t or clear is done at top. see ?fast pwm mode? on page 105 for more details. table 12-4 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 107 for more details. ? bit 2:0 ? cs02:0: clock select the three clock select bits select the cloc k source to be used by the timer/counter. if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an outpu t. this feature allows software control of the counting. 12.9.2 timer/counter0 register ? tcnt0 the timer/counter register gives direct ac cess, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt0 register blocks (removes) the compare match on the following timer clock. modifying t he counter (tcnt0) while the counter is running, introduces a risk of missing a compare match between tcnt0 and the ocr0a register. table 12-4. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01reserved 10 clear oc0a on compare match when up-counting. set oc0a on compare match when downcounting. 11 set oc0a on compare match when up-counting. clear oc0a on compare match when downcounting. table 12-5. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 tcnt0[7:0] tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 112 7679h?can?08/08 at90can32/64/128 12.9.3 output compare register a ? ocr0a the output compare register a contains an 8-bi t value that is conti nuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0a pin. 12.9.4 timer/counter0 interrupt mask register ? timsk0 ? bit 7..2 ? reserved bits these are reserved bits for future use. ? bit 1 ? ocie0a: timer/counter0 output compare match a interrupt enable when the ocie0a bit is written to one, and the i-bit in the status register is set (one), the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter0 occurs , i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one, and the i- bit in the status register is set (one), the timer/counter0 overflow interr upt is enabled. the corresponding interrupt is executed if an overflow in timer/counter0 occu rs, i.e., when the tov0 bit is set in the timer/counter 0 inter- rupt flag register ? tifr0. 12.9.5 timer/counter0 interrupt flag register ? tifr0 ? bit 1 ? ocf0a: output compare flag 0 a the ocf0a bit is set (one) when a compare match occurs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the corresponding interrupt handling vector. alter natively, ocf0a is clear ed by writing a logic one to the flag. when the i-bit in sreg, oc ie0a (timer/counter0 compare match interrupt enable), and ocf0a are set (one), the timer/co unter0 compare match interrupt is executed. ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set (one) when an overflow occu rs in timer/counter0. to v0 is cleared by hard- ware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sr eg i-bit, toie0 (timer/counter0 overflow inter- rupt enable), and tov0 are set (one), the timer/ counter0 overflow interrupt is executed. in phase correct pwm mode, this bit is set when timer/counter0 changes counting direction at 0x00. bit 76543210 ocr0a[7:0] ocr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? ? ? ? ? ocie0a toie0 timsk0 read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ??????ocf0a tov0 tifr0 read/write r r r r r r r/w r/w initial value00000000 113 7679h?can?08/08 at90can32/64/128 13. 16-bit timer/counter (timer /counter1 and timer/counter3) the 16-bit timer/counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. the main features are: 13.1 features ? true 16-bit design (i.e., allows 16-bit pwm) ? three independent output compare units ? double buffered output compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? external event counter ? four independent interrupt sources (tov1, ocf1a, ocf1b, and icf1 for timer/counter1 - tov3, ocf3a, ocf3b, and icf3 for timer/counter3) 13.2 overview many register and bit references in this section are written in general form. ? a lower case ?n? replaces the timer/counter number, in this case 1 or 3. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 c ounter value and so on. ? a lower case ?x? replaces the output compare unit channel, in this case a, b or c. however, when using the register or bit defines in a program, the precise form must be used, i.e., ocrna for accessing timer/countern output compare channel a value and so on. a simplified block diagram of the 16-bit timer/counter is shown in figure 13-1 . for the actual placement of i/o pins, refer to ?pin configurations? on page 5 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit loca- tions are listed in the ?16-bit timer/counter register description? on page 135 . 114 7679h?can?08/08 at90can32/64/128 figure 13-1. 16-bit timer/counter block diagram (1) note: 1. refer to figure 1-2 on page 5 or figure 1-3 on page 6 , table 9-6 on page 76 , and table 9-15 on page 83 for timer/counter 1 and 3 pin placement and description. 13.2.1 registers the timer/counter (tcntn), output compare registers (ocrnx), and input capture register (icrn) are all 16-bit registers. special procedures must be followed when accessing the 16-bit registers. these procedures are described in the section ?accessing 16-bit registers? on page 116 . the timer/counter control registers (t ccrnx) are 8-bit registers and have no cpu access restrictions. interrup t requests (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag regist er (tifrn). all interrupts are individually masked with the timer interrupt mask register (t imskn). tifrn and timskn are not shown in the figure. the timer/counter can be clocked internally, via th e prescaler, or by an external clock source on the tn pin. the clock select logic block contro ls which clock source and edge the timer/counter icfn (int.req.) tovn (int.req.) clock select timer/counter databus ocrna ocrnb ocrnc icrn = = = tcntn waveform generation waveform generation waveform generation ocna ocnb ocnc noise canceler icpn = fixed top values edge detector control logic = 0 top bottom count clear direction ocfna (int.req.) ocfnb (int.req.) ocfnc (int.req.) tccrna tccrnb tccrnc ( from analog comparator ouput ) tn edge detector ( from prescaler ) clk tn 115 7679h?can?08/08 at90can32/64/128 uses to increment (or decrement) its value. th e timer/counter is inactive when no clock source is selected. the output from th e clock select logic is referred to as the timer clock (clk t n ). the double buffered output compare registers (ocrnx) are compared with the timer/counter value at all time. the result of the compare ca n be used by the waveform generator to generate a pwm or variable frequency output on the output compare pin (ocnx). see ?output compare units? on page 123. . the compare match event will also set the compare match flag (ocfnx) which can be used to generate an output compare interrupt request. the input capture register can c apture the timer/counter value at a given external (edge trig- gered) event on either the input capture pin (icpn) or on the analog comparator pins ( see ?analog comparator? on page 269. ) the input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter valu e, can in some modes of operation be defined by either the ocrna register, the icrn regist er, or by a set of fixed values. when using ocrna as top value in a pwm mode, the ocrna register can not be used for generating a pwm output. however, the top value will in this case be do uble buffered allowing the top value to be changed in run time. if a fixed top value is required, the icrn register can be used as an alternative, freeing the ocrna to be used as pwm output. 13.2.2 definitions the following definitions are used ex tensively throughout the section: 13.2.3 compatibility the 16-bit timer/counter has been updated and impr oved from previous versions of the 16-bit avr timer/counter. this 16-bit timer/counter is fully compatible with the earlier version regarding: ? all 16-bit timer/counter related i/o register address locations, including timer interrupt registers. ? bit locations inside all 16-bit timer/counter registers, incl uding timer interrupt registers. ? interrupt vectors. the following control bits have changed name, but have same functionality and register location: ? pwmn0 is changed to wgmn0. ? pwmn1 is changed to wgmn1. ? ctcn is changed to wgmn2. the following registers are added to the 16-bit timer/counter: ? timer/counter control register c (tccrnc). ? output compare register c, o crnch and ocrncl, combined ocrnc. bottom the counter reaches the bottom when it becomes 0x0000. max the counter reaches its maximum when it becomes 0xffff (decimal 65,535). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be one of the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the ocr n a or icr n register. the assignment is dependent of the m ode of operation. 116 7679h?can?08/08 at90can32/64/128 the 16-bit timer/counter has improvements that will affect the compatibility in some special cases. the following bits are added to the 16-bit timer/counter control registers: ? comnc1:0 are added to tccrna. ? focna, focnb and focnc are added to tccrnc. ? wgmn3 is added to tccrnb. interrupt flag and mask bits for output compare unit c are added. the 16-bit timer/counter has improvements that will affect the compatibility in some special cases. 13.3 accessing 16-bit registers the tcntn, ocrnx, and icrn are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit regist er in the same clock cycle. when the low byte of a 16-bit register is read by the cpu, the high by te of the 16-bit register is copied into the tempo- rary register in the same clock cycle as the low byte is read. not all 16-bit accesses uses the temporary register for the high byte. reading the ocrnx 16-bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. 117 7679h?can?08/08 at90can32/64/128 13.3.1 code examples the following code examples show how to acce ss the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocrnx and icrn registers. note that wh en using ?c?, the compiler handles the 16-bit access. note: 1. the example code assumes that the part specific header file is included. the assembly code example returns the t cntn value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the sa me or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. assembly code examples (1) ... ; set tcntn to 0x01ff ldi r17,0x01 ldi r16,0xff sts tcntnh,r17 sts tcntnl,r16 ; read tcntn into r17:r16 lds r16,tcntnl lds r17,tcntnh ... c code examples (1) unsigned int i; ... /* set tcntn to 0x01ff */ tcnt n = 0x1ff; /* read tcntn into i */ i = tcntn; ... 118 7679h?can?08/08 at90can32/64/128 the following code examples show how to do an atomic read of the tcntn register contents. reading any of the ocrnx or icrn register s can be done by using the same principle. note: 1. the example code assumes that the part specific header file is included. the assembly code example returns the t cntn value in the r17:r16 register pair. assembly code example (1) tim16_readtcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcntn into r17:r16 lds r16,tcntnl lds r17,tcntnh ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcntn( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcntn into i */ i = tcntn; /* restore global interrupt flag */ sreg = sreg; return i; } 119 7679h?can?08/08 at90can32/64/128 the following code examples show how to do an at omic write of the tcntn register contents. writing any of the ocrnx or icrn register s can be done by using the same principle. note: 1. the example code assumes that the part specific header file is included. the assembly code example requires that the r17: r16 register pair contains the value to be writ- ten to tcntn. 13.3.2 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. 13.4 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (csn2:0) bits located in the timer/counter control register b (tccrnb). for details on clock sources and prescaler, see ?timer/counter3/1/0 prescalers? on page 96 . assembly code example (1) tim16_writetcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcntn to r17:r16 sts tcntnh,r17 sts tcntnl,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcntn( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcntn to i */ tcntn = i; /* restore global interrupt flag */ sreg = sreg; } 120 7679h?can?08/08 at90can32/64/128 13.5 counter unit the main part of the 16-bit timer/counter is th e programmable 16-bit bi-directional counter unit. figure 13-2 shows a block diagram of the counter and its surroundings. figure 13-2. counter unit block diagram signal description (internal signals): count increment or decrement tcntn by 1. direction select between increment and decrement. clear clear tcntn (set all bits to zero). clk t n timer/counter clock. top signalize that tcntn has reached maximum value. bottom signalize that tcntn has re ached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcntnh) con- taining the upper eight bits of the counter, an d counter low (tcntnl) containing the lower eight bits. the tcntnh register can only be indirect ly accessed by the cpu. when the cpu does an access to the tcntnh i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tcntnh value when the tcntnl is read, and tcntnh is updated with the temporary register va lue when tcntnl is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcntn register when the counter is counting that will gi ve unpredictable results. the s pecial cases are described in the sections where they are of importance. depending on the mode of operation used, the co unter is cleared, incremented, or decremented at each timer clock (clk t n ). the clk t n can be generated from an external or internal clock source, selected by the clock select bits (csn2:0). w hen no clock source is selected (csn2:0 = 0) the timer is stopped. however, the tcntn value can be accessed by the cpu, independent of whether clk t n is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the waveform generation mode bits (wgmn3:0) located in the timer/counter c ontrol registers a and b (tccrna and tccrnb). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs ocnx. for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 126 . temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear direction tovn (int.req.) clock select top bottom tn edge detector ( from prescaler ) clk tn 121 7679h?can?08/08 at90can32/64/128 the timer/counter overflow flag (tovn) is set a ccording to the mode of operation selected by the wgmn3:0 bits. tovn can be us ed for generating a cpu interrupt. 13.6 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an event, or mul- tiple events, can be applied via the icpn pin or al ternatively, via the anal og-comparator unit. the time-stamps can then be used to calculate frequenc y, duty-cycle, and other features of the sig- nal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 13-3 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. figure 13-3. input capture unit block diagram note: the analog comparator output (aco) can only trigger the timer/counter1 ic unit? not timer/counter3. when a change of the logic level (an event) occurs on the input capture pin (icpn), alternatively on the analog comparator output (aco), and th is change confirms to the setting of the edge detector, a capture will be triggered. when a captur e is triggered, the 16-bit value of the counter (tcntn) is written to the input capture register (icrn). the input capture flag (icfn) is set at the same system clock as the tcntn value is copi ed into icrn register. if enabled (icien = 1), the input capture flag generates an input capt ure interrupt. the icfn flag is automatically write icrn (16-bit register) icrnh (8-bit) temp (8-bit) data bus (8-bit) icrnl (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) icf1 (int.req.) noise canceler edge detector acic* icnc1 ices1 icp1 analog comparator aco* icf3 (int.req.) noise canceler icp3 edge detector icnc3 ices3 122 7679h?can?08/08 at90can32/64/128 cleared when the interrupt is executed. alternativ ely the icfn flag can be cleared by software by writing a logical one to its i/o bit location. reading the 16-bit value in the input capture register (icrn) is done by first reading the low byte (icrnl) and then the high byte (icrnh). when the low byte is read the high byte is copied into the high byte temporary regi ster (temp). when th e cpu reads the icrnh i/o location it will access the temp register. the icrn register can only be written when using a waveform generation mode that utilizes the icrn register for defining the counter?s top value. in these cases the waveform genera- tion mode (wgmn3:0) bits must be set before the top value can be written to the icrn register. when writing the icrn re gister the high byte must be written to the icrnh i/o location before the low byte is written to icrnl. for more information on how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 116 . 13.6.1 input capture trigger source the main trigger source for the input capture unit is the input capture pin (icpn). only timer/counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture (acic) bit in the analog comparator control and status register (acsr). be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icpn) and the anal og comparator output (aco) inputs are sampled using the same technique as for the tn pin ( figure 11-1 on page 97 ). the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases t he delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabl ed unless the timer/counter is set in a wave- form generation mode that uses icrn to define top. an input capture can be trigger ed by software by controlling the port of the icpn pin. 13.6.2 noise canceler the noise canceler improves noise immunity by using a simple digita l filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input captur e noise canceler (icncn) bit in timer/counter control register b (tccrnb). when enabled the noise canceler introduces addi- tional four system clock cycles of delay from a change applied to the input, to the update of the icrn register. the noise canceler uses the sy stem clock and is therefore not affected by the prescaler. 13.6.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured valu e in the icrn register before th e next event occurs, the icrn will be overwritten with a new value. in this case the result of the ca pture will be incorrect. when using the input capture in terrupt, the icrn register shoul d be read as early in the inter- rupt handler routine as possible. even though the input capture interrupt has relatively high 123 7679h?can?08/08 at90can32/64/128 priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icrn register has been read. after a change of the edge, the input capture flag (icfn) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of the icfn flag is not r equired (if an interrupt handler is used). 13.7 output compare units the 16-bit comparator continuously compares tcntn with the output compare register (ocrnx). if tcnt equals ocrnx the comparator signals a match. a match will set the output compare flag (ocfnx) at the next timer clock c ycle. if enabled (ocienx = 1), the output com- pare flag generates an output compare interrupt. the ocfnx flag is automatically cleared when the interrupt is executed. al ternatively the ocfnx flag can be cleared by software by writ- ing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode (wgmn3:0) bits and compare output mode (c omnx1:0) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( see ?modes of operation? on page 126. ) a special feature of output comp are unit a allows it to define the timer/counter top value (i.e., counter resolution). in addition to the counter resolution, the top val ue defines the period time for waveforms generated by the waveform generator. figure 13-4 shows a block diagram of the output co mpare unit. the elements of the block dia- gram that are not directly a part of the output compare unit are gray shaded. 124 7679h?can?08/08 at90can32/64/128 figure 13-4. output compare unit, block diagram the ocrnx register is double buffered when us ing any of the twelve pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buff ering synchronizes the update of the ocrnx com- pare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the out- put glitch-free. the ocrnx register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocrnx buffer register, and if double buffering is dis- abled the cpu will access the ocrnx directly. the content of the ocrnx (buffer or compare) register is only changed by a write operation (the timer/counter does not update this register automatically as the tcnt1 and icrn register). therefore ocrnx is not read via the high byte temporary register (temp). however, it is a good practice to read the low byte first as when accessing other 16-bit registers. writing the oc rnx registers must be done via the temp reg- ister since the compare of all 16 bits is done continuously. the high byte (ocrnxh) has to be written first. when the high byte i/o location is written by the cpu, the temp register will be updated by the value written. then when the low by te (ocrnxl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocrnx bu ffer or ocrnx compare register in the same system clock cycle. for more information of how to acce ss the 16-bit registers refer to ?accessing 16-bit registers? on page 116 . 13.7.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force outp ut compare (focnx) bit. forci ng compare match will not set the ocfnx flag or reload/clear the timer, but the ocnx pin will be updated as if a real compare ocfnx (int.req.) = (16-bit comparator ) ocrnx buffer (16-bit register) ocrnxh buf.(8-bit) ocnx temp (8-bit) data bus (8-bit) ocrnxl buf.(8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) comnx1:0 wgmn3:0 ocrnx (16-bit register) ocrnxh (8-bit) ocrnxl (8-bit) waveform generator top bottom 125 7679h?can?08/08 at90can32/64/128 match had occurred (the comnx1:0 bits settings de fine whether the ocnx pin is set, cleared or toggled). 13.7.2 compare match blocking by tcntn write all cpu writes to the tcntn register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocrnx to be initialized to the same value as tcntn without triggering an inte rrupt when the timer/counter clock is enabled. 13.7.3 using the output compare unit since writing tcntn in any mode of operation will block all comp are matches for one timer clock cycle, there are risks involved when changi ng tcntn when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcntn equals the ocrnx value, the compare matc h will be missed, resulting in incorrect wave- form generation. do not write the tcntn equal to top in pwm modes with variable top values. the compare match for the top will be ignored and the counte r will continue to 0xffff. similarly, do not write the tcntn value equal to bottom when the counter is downcounting. the setup of the ocnx should be performed befor e setting the data dire ction register for the port pin to output. the easiest way of setting the ocnx value is to use the force output com- pare (focnx) strobe bits in normal mode. t he ocnx register keeps its value even when changing between waveform generation modes. be aware that the comnx1:0 bits are not double buffered together with the compare value. changing the comnx1:0 bits will take effect immediately. 13.8 compare match output unit the compare output mode (comnx1:0) bits ha ve two functions. the waveform generator uses the comnx1:0 bits for defining the output co mpare (ocnx) state at the next compare match. secondly the comnx1:0 bits control the ocnx pin output source. figure 13-5 shows a simplified schematic of the logic affected by the comnx1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the comnx1:0 bits are shown. when referring to the ocnx state, the reference is for the internal ocnx re gister, not the ocnx pin. if a system reset occur, the ocnx register is reset to ?0?. 126 7679h?can?08/08 at90can32/64/128 figure 13-5. compare match output unit, schematic 13.8.1 compare output function the general i/o port function is overridden by the output compare (ocnx) from the waveform generator if either of the comnx1:0 bits are se t. however, the ocnx pin direction (input or out- put) is still controlled by the da ta direction register (ddr) for th e port pin. the data direction register bit for the ocnx pin (ddr_ocnx) must be set as output before th e ocnx value is visi- ble on the pin. the port overri de function is generally indep endent of the waveform generation mode, but there are some exceptions. refer to table 13-1 , table 13-2 and table 13-3 for details. the design of the output compare pin logic allows initialization of the oc nx state before the out- put is enabled. note that some comnx1:0 bi t settings are reserved for certain modes of operation. see ?16-bit timer/counter regist er description? on page 135. the comnx1:0 bits have no effect on the input capture unit. 13.8.2 compare output mode and waveform generation the waveform generator uses the comnx1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the comn x1:0 = 0 tells the waveform generator that no action on the ocnx register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 13-1 on page 136 . for fast pwm mode refer to table 13-2 on page 136 , and for phase correct and phase and frequency correct pwm refer to table 13-3 on page 137 . a change of the comnx1:0 bits st ate will have effect at the first compare match after the bits are written. for non-pwm modes, the action can be fo rced to have immediate effect by using the focnx strobe bits. 13.9 modes of operation the mode of operation, i.e., t he behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgmn3:0) and compare output mode (comnx1:0) bits. the compare output mode bits do not affect the counting sequence, port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data bus focnx clk i/o 127 7679h?can?08/08 at90can32/64/128 while the waveform generation mode bits do. the comnx1:0 bits control whether the pwm out- put generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the comnx1:0 bits control whether the output should be set, cleared or toggle at a compare match ( see ?compare match output unit? on page 125. ) for detailed timing information refer to ?timer/counter timing diagrams? on page 134 . 13.9.1 normal mode the simplest mode of operation is the normal mode (wgmn3:0 = 0). in this mode the counting direction is always up (incre menting), and no counter clear is performed. the counter simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/c ounter overflow flag (tovn) will be set in the same timer clock cycle as the tcntn beco mes zero. the tovn flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tovn flag , the timer resolution ca n be increased by soft- ware. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. however, observe that the maximum interval between the external events must not exceed the resolution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generat e interrupts at some given time. using the output compare to gene rate waveforms in norm al mode is not recommended, since this will occupy too much of the cpu time. 13.9.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgmn3:0 = 4 or 12), the ocrna or icrn register are used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcntn) matches either the oc rna (wgmn3:0 = 4) or the icrn (wgmn3:0 = 12). the ocrna or icrn define the top value for the counter, hence also its resolution. this mode allows greater control of the compare match ou tput frequency. it also simplifies the opera- tion of counting external events. the timing diagram for the ctc mode is shown in figure 13-6 . the counter value (tcntn) increases until a compare match occurs with ei ther ocrna or icrn, and then counter (tcntn) is cleared. figure 13-6. ctc mode, timing diagram tcntn ocna (toggle) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 4 period 2 3 (comna1:0 = 1) 128 7679h?can?08/08 at90can32/64/128 an interrupt can be generated at each time the counter value reaches the top value by either using the ocfna or icfn flag according to the re gister used to define the top value. if the inter- rupt is enabled, the interrupt handler routine ca n be used for updating the top value. however, changing the top to a value close to bottom w hen the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocrna or icrn is lowe r than the current value of tcntn, the counter will miss the compare matc h. the counter will th en have to count to its maximum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is not desirable. an alternativ e will then be to use the fast pwm mode using ocrna for defining top (wgmn3:0 = 15) si nce the ocrna then will be double buffered. for generating a waveform output in ctc mode, t he ocna output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (comna1:0 = 1). the ocna value will not be visible on the port pin unless the data direction for the pin is set to output (ddr_ocna = 1). th e waveform generated will have a maximum fre- quency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0 x0000). the wavefo rm frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tovn flag is set in the same time r clock cycle that the counter counts from max to 0x0000. 13.9.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgmn3:0 = 5, 6, 7, 14, or 15) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (ocnx) is set on the compare match between tcntn and ocrnx, and cleared at top. in inverting compare output mode output is cleared on compare match and set at top. due to the single-slope oper- ation, the operating frequency of the fast pwm mo de can be twice as high as the phase correct and phase and frequency correct pwm modes that use dual-slope operation. this high fre- quency makes the fast pwm mode well suited fo r power regulation, re ctification, and dac applications. high frequency allows physically sm all sized external com ponents (coils, capaci- tors), hence reduces total system cost. the pwm resolution for fast pwm can be fixed to 8- , 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the max- imum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated by using the following equation: in fast pwm mode the co unter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 5, 6, or 7), the value in icrn (wgmn3:0 = 14), or the value in ocrna (wgmn3:0 = 15). th e counter is then cleared at the following timer clock cycle. the timing diagram fo r the fast pwm mode is shown in figure 13-7 . the figure f ocna f clk_i/o 2 n 1 ocrna + () ?? -------------------------------------------------- - = r fpwm top 1 + () log 2 () log ---------------------------------- - = 129 7679h?can?08/08 at90can32/64/128 shows fast pwm mode when ocrna or icrn is us ed to define top. the tcntn value is in the timing diagram shown as a histogram for illu strating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare matc hes between ocrnx and tcntn. the ocnx interrupt flag will be set when a compare match occurs. figure 13-7. fast pwm mode, timing diagram the timer/counter overflow flag (tovn) is set each time the counter reaches top. in addition the ocna or icfn flag is set at the same timer clock cycle as tovn is set when either ocrna or icrn is used for defining the top value. if one of the interrupts are enabled, the interrupt han- dler routine can be used for updating the top and compare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between th e tcntn and the ocrnx. note that when using fixed top values the unused bits are masked to zero when any of the ocrnx registers are written. the procedure for updating icrn differs from updating ocrna when used for defining the top value. the icrn register is not double buffered. this means that if icrn is changed to a low value when the counter is running with none or a lo w prescaler value, there is a risk that the new icrn value written is lower than the current va lue of tcntn. the result will then be that the counter will miss the compare matc h at the top value. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. the ocrna register however, is double buffered. this feature allows the ocrna i/o location to be written anytime. when the ocrna i/o location is written the value written will be put into the ocrna buffer register. th e ocrna compare register will th en be updated with the value in the buffer register at the next timer clo ck cycle the tcntn matches top. the update is done at the same timer clock cycle as the tcnt n is cleared and the tovn flag is set. using the icrn register for defining top work s well when using fixed top values. by using icrn, the ocrna register is free to be used for generating a pwm output on ocna. however, if the base pwm frequency is actively change d (by changing the top value), using the ocrna as top is clearly a better choice due to its double buffer feature. tcntn ocrnx/top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 130 7679h?can?08/08 at90can32/64/128 in fast pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 136 ). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx register at the compare match between ocrnx and tcntn, and clearing (or setting) the ocnx register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register re presents special cases when generating a pwm waveform output in the fast pwm mode. if the ocrnx is set equal to bottom (0x0000) the out- put will be a narrow spike for ea ch top+1 timer clock cycle. se tting the ocrnx equal to top will result in a const ant high or low output (depending on the polarity of the output set by the comnx1:0 bits.) a frequency (with 50% duty cycle) waveform out put in fast pwm mode can be achieved by set- ting ocna to toggle its logical level on each compare match (comna1:0 = 1). the waveform generated will have a maximum frequency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0x0000). this feature is similar to the ocna to ggle in ctc mode, except the double buffer fea- ture of the output compare unit is enabled in the fast pwm mode. 13.9.4 phase correct pwm mode the phase correct pulse width modulation or phase correct pwm mode (wgmn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual- slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feat ure of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolu- tion in bits can be calculated by using the following equation: in phase correct pwm mode the counter is incr emented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x 03ff (wgmn3:0 = 1, 2, or 3), the value in icrn (wgmn3:0 = 10), or the value in ocrna (wgmn3:0 = 11). the counter has then reached the top and changes the count direct ion. the tcntn value will be equa l to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 13-8 . the figure shows phase correct pwm mode when ocrna or icrn is used to define top. the tcntn f ocnxpwm f clk_i/o n 1 top + () ? ---------------------------------- - = r pcpwm top 1 + () log 2 () log ---------------------------------- - = 131 7679h?can?08/08 at90can32/64/128 value is in the timing diagram shown as a histogram for illustrati ng the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare matches between ocrnx and tcntn. the ocnx inter- rupt flag will be set when a compare match occurs. figure 13-8. phase correct pwm mode, timing diagram the timer/counter overflow flag (tovn) is se t each time the counter reaches bottom. when either ocrna or icrn is used for defining the to p value, the ocna or icfn flag is set accord- ingly at the same timer clock cycle as the ocrnx registers are updated with the double buffer value (at top). the interr upt flags can be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between th e tcntn and the ocrnx. note that when using fixed top values, the unus ed bits are masked to zero when any of the ocrnx registers are written. as the third period shown in figure 13-8 illustrates, changing the top actively while the timer/counter is runni ng in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of update of the ocrnx reg- ister. since the ocrnx update occurs at top, the pwm period starts and ends at top. this implies that the length of the falling slope is determined by the previous top value, while the length of the rising slope is determined by th e new top value. when thes e two values differ the two slopes of the period will differ in length. the difference in length gives the unsymmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the top value while the timer/counter is running. when using a static top value there are practically no differ ences between the two modes of operation. in phase correct pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to tw o will produce a non-inverte d pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 137 ). the actual ocnx value will only be visible on the port pi n if the data direction for the port pin is set as ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tovn interrupt flag set (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 132 7679h?can?08/08 at90can32/64/128 output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx regis- ter at the compare match between ocrnx and tcntn when the counter increments, and clearing (or setting) the ocnx register at compare match between ocrnx and tcntn when the counter decrements. the pw m frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represent special cases when generating a pwm waveform output in the phase correct pwm m ode. if the ocrnx is set equal to bottom the output will be continuously low and if set equal to top the output will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. 13.9.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct pwm mode (wgmn3:0 = 8 or 9) provides a high reso lution phase and frequency correct pwm wave- form generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx while upcounting, and set on the compare match while downcounting. in inverting compare output mode, the operation is inverted. the dual-slope operation gives a lower maximum operation fre- quency compared to the single-slope operation. howe ver, due to the symme tric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the main difference between the phase correct, and the phase and frequency correct pwm mode is the time the ocrnx register is up dated by the ocrnx buffer register, (see figure 13- 8 and figure 13-9 ). the pwm resolution for the phase and frequency correct pwm mode can be defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrn a set to max). the pwm re solution in bits can be calculated using the following equation: in phase and frequency correct pwm mode the counter is incremented until the counter value matches either the value in icrn (wgmn3:0 = 8), or the value in ocrna (wgmn3:0 = 9). the counter has then reac hed the top and ch anges the count di rection. the tcntn value will be equal to top for one timer clock cycle. the timi ng diagram for the phase correct and frequency correct pwm mode is shown on figure 13-9 . the figure shows phase and frequency correct pwm mode when ocrna or icrn is used to defi ne top. the tcntn value is in the timing dia- gram shown as a histogram for illustrating the dual-slope operati on. the diagram includes non- inverted and inverted pwm outputs. the small hor izontal line marks on t he tcntn slopes repre- sent compare matches between oc rnx and tcntn. the ocnx inte rrupt flag will be set when a compare match occurs. f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------- - = r pfcpwm top 1 + () log 2 () log ---------------------------------- - = 133 7679h?can?08/08 at90can32/64/128 figure 13-9. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tovn) is se t at the same timer clock cycle as the ocrnx registers are updated with the double buffer value (at bottom). when either ocrna or icrn is used for defining the top value, the ocna or icfn flag set when tcntn has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will neve r occur between the tcntn and the ocrnx. as figure 13-9 shows the output generated is, in contra st to the phase correct mode, symmetri- cal in all periods. since the ocrnx registers are updated at bottom, the length of the rising and the falling slopes will always be equal. this gives symmetrical output pulses and is therefore frequency correct. using the icrn register for defining top work s well when using fixed top values. by using icrn, the ocrna register is free to be used for generating a pwm output on ocna. however, if the base pwm frequency is actively change d by changing the top value, using the ocrna as top is clearly a better choice due to its double buffer feature. in phase and frequency correct pwm mode, the compare units allow generation of pwm wave- forms on the ocnx pins. settin g the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 137 ). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx register at the compare match between ocrnx and tcntn when the counter incre- ments, and clearing (or setting) the ocnx register at compare match between ocrnx and tcntn when the counter decrem ents. the pwm frequency for the output when using phase and frequency correct pwm can be calculated by the following equation: ocrnx/top update and tovn interrupt flag set (interrupt on bottom) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------- - = 134 7679h?can?08/08 at90can32/64/128 the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register re presents special cases when generating a pwm waveform output in the phase correct pwm m ode. if the ocrnx is set equal to bottom the output will be continuously low and if set equal to top the output will be set to high for non- inverted pwm mode. for inverted pwm the ou tput will have the opposite logic values. 13.10 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk tn ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set, and when the ocrn x register is updated with the ocrnx buffer value (only for modes utilizing double buffering). figure 13-10 shows a timing diagram fo r the setting of ocfnx. figure 13-10. timer/counter timing diagram, setting of ocfnx, no prescaling figure 13-11 shows the same timing data, but with the prescaler enabled. figure 13-11. timer/counter timing diagram, setting of ocfnx, with prescaler (f clk_i/o /8) figure 13-12 shows the count sequence close to top in various modes. when using phase and frequency correct pwm mode the ocrnx register is updated at bottom. the timing diagrams will be the same, but top should be replaced by bottom, top-1 by bottom+1 and so on. the same renaming applies for modes that set the tovn flag at bottom. clk tn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 135 7679h?can?08/08 at90can32/64/128 figure 13-12. timer/counter timing diagram, no prescaling figure 13-13 shows the same timing data, but with the prescaler enabled. figure 13-13. timer/counter timing diagram, with prescaler (f clk_i/o /8) 13.11 16-bit timer/counte r register description 13.11.1 timer/counter1 cont rol register a ? tccr1a 13.11.2 timer/counter3 cont rol register a ? tccr3a tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 7 6 5 4 3210 com1a1 com1a0 com1b1 com1b0 co m1c1 com1c0 wgm11 wgm10 tccr1a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3210 com3a1 com3a0 com3b1 com3b0 co m3c1 com3c0 wgm31 wgm30 tccr3a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 136 7679h?can?08/08 at90can32/64/128 ? bit 7:6 ? comna1:0: compare output mode for channel a ? bit 5:4 ? comnb1:0: compare output mode for channel b ? bit 3:2 ? comnc1:0: compare output mode for channel c the comna1:0, comnb1:0 and comnc1:0 control the output compare pins (ocna, ocnb and ocnc respectively) behavior. if one or both of the comna1:0 bits are written to one, the ocna output overrides the normal port functionality of the i/o pin it is connected to. if one or both of the comnb1:0 bit are wr itten to one, the ocnb output overrides the normal port func- tionality of the i/o pin it is connected to. if on e or both of the comnc1:0 bit are written to one, the ocnc output overrides the normal port functi onality of the i/o pin it is connected to. how- ever, note that the data direction register (ddr) bit corresponding to the ocna, ocnb or ocnc pin must be set in order to enable the output driver. when the ocna, ocnb or ocnc is connected to the pin, the function of the comnx1:0 bits is dependent of the wgmn3:0 bits setting. table 13-1 shows the comnx1:0 bit functionality when the wgmn3:0 bits are set to a normal or a ctc mode (non-pwm). table 13-2 shows the comnx1:0 bit functionality when the wgmn3:0 bits are set to the fast pwm mode. note: 1. a special case occurs when ocrna/ocrnb/ocrnc equals top and comna1/comnb1/comnc1 is set. in this case the compare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 128. for more details. table 13-1. compare output mode, non-pwm comna1/comnb1/ comnc1 comna0/comnb0/ comnc0 description 00 normal port operation, ocna/ocnb/ocnc disconnected. 0 1 toggle ocna/ocnb/ocnc on compare match. 10 clear ocna/ocnb/ocnc on compare match (set output to low level). 11 set ocna/ocnb/ocnc on compare match (set output to high level). table 13-2. compare output mode, fast pwm (1) comna1/comnb1/ comnc1 comna0/comnb0/ comnc0 description 00 normal port operation, ocna/ocnb/ocnc disconnected. 01 wgmn3=0: normal port operation, ocna/ocnb/ocnc disconnected. wgmn3=1: toggle ocna on compare match, ocnb/ocnc reserved. 10 clear ocna/ocnb/ocnc on compare match set ocna/ocnb/ocnc at top 11 set ocna/ocnb/ocnc on compare match clear ocna/ocnb/ocnc at top 137 7679h?can?08/08 at90can32/64/128 table 13-3 shows the comnx1:0 bit functionality w hen the wgmn3:0 bits are set to the phase correct or the phase and frequency correct, pwm mode. note: 1. a special case occurs when ocna/ocnb/ocnc equals top and comna1/comnb1/comnc1 is set. see ?phase correct pwm mode? on page 130. for more details. ? bit 1:0 ? wgmn1:0: waveform generation mode combined with the wgmn3:2 bits found in the tc crnb register, these bits control the counting sequence of the counter, the source for maximu m (top) counter value, and what type of wave- form generation to be used, see table 13-4 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and three types of pulse width modulation (pwm) modes. ( see ?modes of operation? on page 126. ). table 13-3. compare output mode, phase correct and phase and frequency correct pwm (1) comna1/comnb1/ comnc1 comna0/comnb0/ comnc0 description 00 normal port operation, ocna/ocnb/ocnc disconnected. 01 wgmn3=0: normal port operation, ocna/ocnb/ocnc disconnected. wgmn3=1: toggle ocna on compare match, ocnb/ocnc reserved. 10 clear ocna/ocnb/ocnc on compare match when up-counting. set ocna/ocnb/ocnc on compare match when downcounting. 11 set ocna/ocnb/ocnc on compare match when up- counting. clear ocna/ocnb/ocnc on compare match when downcounting. 138 7679h?can?08/08 at90can32/64/128 note: 1. the ctcn and pwmn1:0 bit definition names are obsolete. use the wgm n2:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. 13.11.3 timer/counter1 cont rol register b ? tccr1b 13.11.4 timer/counter3 cont rol register b ? tccr3b ? bit 7 ? icncn: input capture noise canceler setting this bit (to one) activates the input capt ure noise canceler. when the noise canceler is activated, the input from the inpu t capture pin (icpn) is filtered. the filter function requires four successive equal valued samples of the icpn pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. ? bit 6 ? icesn: input capture edge select table 13-4. waveform generation mode bit description (1) mode wgmn3 wgmn2 (ctcn) wgmn1 (pwmn1) wgmn0 (pwmn0) timer/counter mode of operation top update of ocrnx at tovn flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bottom 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bottom 30011 pwm, phase correct, 10- bit 0x03ff top bottom 4 0 1 0 0 ctc ocrna immediate max 5 0 1 0 1 fast pwm, 8-bit 0x00ff top top 6 0 1 1 0 fast pwm, 9-bit 0x01ff top top 7 0 1 1 1 fast pwm, 10-bit 0x03ff top top 81000 pwm, phase and frequency correct icrn bottom bottom 91001 pwm, phase and frequency correct ocrna bottom bottom 10 1 0 1 0 pwm, phase correct icrn top bottom 11 1 0 1 1 pwm, phase correct ocrna top bottom 12 1 1 0 0 ctc icrn immediate max 13 1 1 0 1 (reserved) ? ? ? 141110fast pwm icrntop top 15 1 1 1 1 fast pwm ocrna top top bit 7654 3210 icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7654 3210 icnc3 ices3 ? wgm33 wgm32 cs32 cs31 cs30 tccr3b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 139 7679h?can?08/08 at90can32/64/128 this bit selects which edge on the input capture pin (icpn) that is used to trigger a capture event. when the icesn bit is written to zero, a falling (negative) edge is used as trigger, and when the icesn bit is written to one, a risi ng (positive) edge w ill trigger the capture. when a capture is triggered according to the icesn setting, the counter value is copied into the input capture register (icrn). the event will also set the input capture flag (icfn), and this can be used to cause an input capture in terrupt, if this in terrupt is enabled. when the icrn is used as top value (see description of the wgmn3:0 bits located in the tccrna and the tccrnb register), the icpn is disconnected and consequently the input cap- ture function is disabled. ? bit 5 ? reserved bit this bit is reserved for future use. for ensuring compatibility with future de vices, this bit must be written to zero when tccrnb is written. ? bit 4:3 ? wgmn3:2: waveform generation mode see tccrna register description. ? bit 2:0 ? csn2:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see figure 13-10 and figure 13-11 . if external pin modes are used for the timer/countern, transitions on the tn pin will clock the counter even if the pin is configured as an outpu t. this feature allows software control of the counting. 13.11.5 timer/counter1 cont rol register c ? tccr1c table 13-5. clock select bit description csn2 csn1 csn0 description 0 0 0 no clock source (timer/counter stopped). 001clk i/o /1 (no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on tn pin. clock on falling edge. 1 1 1 external clock source on tn pin. clock on rising edge. bit 7654 3210 foc1a foc1b foc1c ? ? ? ? ? tccr1c read/write r/w r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 140 7679h?can?08/08 at90can32/64/128 13.11.6 timer/counter3 cont rol register c ? tccr3c ? bit 7 ? focna: force output compare for channel a ? bit 6 ? focnb: force output compare for channel b ? bit 5 ? focnc: force output compare for channel c the focna/focnb/focnc bits are only active when the wgmn3:0 bits specifies a non-pwm mode. however, for ensu ring compatibility with future devic es, these bits must be set to zero when tccrna is written when oper ating in a pwm mode. when wr iting a logical one to the focna/focnb/focnc bit, an immediate compare match is forced on the waveform genera- tion unit. the ocna/ocnb/ocnc output is cha nged according to its comnx1:0 bits setting. note that the focna/focnb/focn c bits are implemented as stro bes. therefore it is the value present in the comnx1:0 bits that dete rmine the effect of the forced compare. a focna/focnb/focnc strobe will no t generate any interr upt nor will it clear the timer in clear timer on compare match (ctc) mode using ocrna as top. the focna/focnb/focnc bits are always read as zero. 13.11.7 timer/counter1 ? tcnt1h and tcnt1l 13.11.8 timer/counter3 ? tcnt3h and tcnt3l the two timer/counter i/o locations (tcntn h and tcntnl, combined tcntn) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is perfo rmed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 116. modifying the counter (tcntn) while the counte r is running introduces a risk of missing a com- pare match between tcntn and one of the ocrnx registers. writing to the tcntn register blocks (removes ) the compare match on the following timer clock for all compare units. bit 7654 3210 foc3a foc3b foc3c ? ? ? ? ? tccr3c read/write r/w r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 bit 76543210 tcnt1[15:8] tcnt1h tcnt1[7:0] tcnt1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 tcnt3[15:8] tcnt3h tcnt3[7:0] tcnt3l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 141 7679h?can?08/08 at90can32/64/128 13.11.9 output compare regi ster a ? ocr1ah and ocr1al 13.11.10 output compare regi ster b ? ocr1bh and ocr1bl 13.11.11 output compare regi ster c ? ocr1ch and ocr1cl 13.11.12 output compare regi ster a ? ocr3ah and ocr3al 13.11.13 output compare regi ster b ? ocr3bh and ocr3bl 13.11.14 output compare regi ster c ? ocr3ch and ocr3cl the output compare registers contain a 16-bit value that is continuo usly compared with the counter value (tcntn). a match can be used to generate an output compare interrupt, or to generate a waveform output on the ocnx pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cp u writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this te mporary register is shared by all the other 16- bit registers. see ?accessing 16-bit registers? on page 116. bit 76543210 ocr1a[15:8] ocr1ah ocr1a[7:0] ocr1al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1b[15:8] ocr1bh ocr1b[7:0] ocr1bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1c[15:8] ocr1ch ocr1c[7:0] ocr1cl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr3a[15:8] ocr3ah ocr3a[7:0] ocr3al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr3b[15:8] ocr3bh ocr3b[7:0] ocr3bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr3c[15:8] ocr3ch ocr3c[7:0] ocr3cl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 142 7679h?can?08/08 at90can32/64/128 13.11.15 input capture register ? icr1h and icr1l 13.11.16 input capture register ? icr3h and icr3l the input capture is updated with the counter (tcntn) value each time an event occurs on the icpn pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these regi sters, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 116. 13.11.17 timer/counter1 interrupt mask register ? timsk1 13.11.18 timer/counter3 interrupt mask register ? timsk3 ? bit 7..6 ? reserved bits these bits are reserv ed for future use. ? bit 5 ? icien: input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern input capture interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 60. ) is executed when the icfn flag, located in tifrn, is set. ? bit 4 ? reserved bit this bit is reserv ed for future use. ? bit 3 ? ocienc: output compare c match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern output compare c match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 60. ) is executed when the ocfnc flag, located in tifrn, is set. bit 76543210 icr1[15:8] icr1h icr1[7:0] icr1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 icr3[15:8] icr3h icr3[7:0] icr3l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? icie1 ? ocie1c ocie1b ocie1a toie1 timsk1 read/write r r r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ? ? icie3 ? ocie3c ocie3b ocie3a toie3 timsk3 read/write r r r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 143 7679h?can?08/08 at90can32/64/128 ? bit 2 ? ocienb: output compare b match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern output compare b match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 60. ) is executed when the ocfnb flag, located in tifrn, is set. ? bit 1 ? ociena: output compare a match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern output compare a match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 60. ) is executed when the ocfna flag, located in tifrn, is set. ? bit 0 ? toien: timer/counter overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern overflow interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 60. ) is executed when the tovn flag, located in tifrn, is set. 13.11.19 timer/counter1 interrupt flag register ? tifr1 13.11.20 timer/counter3 interrupt flag register ? tifr3 ? bit 7..6 ? reserved bits these bits are reserv ed for future use. ? bit 5 ? icfn: input capture flag this flag is set when a capture event occurs on the icpn pin. when the input capture register (icrn) is set by the wgmn3:0 to be used as the top value, the icfn flag is set when the counter reaches the top value. icfn is automatically cleared when the input capt ure interrupt vector is executed. alternatively, icfn can be cleared by writing a logic one to its bit location. ? bit 4 ? reserved bit this bit is reserv ed for future use. ? bit 3 ? ocfnc: output compare c match flag this flag is set in the time r clock cycle after the counter (tcntn) value matches the output compare register c (ocrnc). note that a forced output compare (foc nc) strobe will not set the ocfnc flag. ocfnc is automatically cleared when the outp ut compare match c interrupt vector is exe- cuted. alternatively, ocfnc can be cleared by writing a logic one to its bit location. bit 76543210 ? ? icf1 ? ocf1c ocf1b ocf1a tov1 tifr1 read/write r r r/w r r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? icf3 ? ocf3c ocf3b ocf3a tov3 tifr3 read/write r r r/w r r/w r/w r/w r/w initial value00000000 144 7679h?can?08/08 at90can32/64/128 ? bit 2 ? ocfnb: output compare b match flag this flag is set in the time r clock cycle after the counter (tcntn) value matches the output compare register b (ocrnb). note that a forced output compare (foc nb) strobe will not set the ocfnb flag. ocfnb is automatically cleare d when the output compare matc h b interrupt vector is exe- cuted. alternatively, ocfnb can be cleared by writing a logic one to its bit location. ? bit 1 ? ocfna: output compare a match flag this flag is set in the time r clock cycle after the counter (tcntn) value matches the output compare register a (ocrna). note that a forced output compare (foc na) strobe will not set the ocfna flag. ocfna is automatically cleare d when the output compare matc h a interrupt vector is exe- cuted. alternatively, ocfna can be cleared by writing a logic one to its bit location. ? bit 0 ? tovn: timer/counter overflow flag the setting of this flag is dependent of the wg mn3:0 bits setting. in normal and ctc modes, the tovn flag is set when the timer overflows. refer to table 13-4 on page 138 for the tovn flag behavior when using a nother wgmn3:0 bit setting. tovn is automatically cleared when the timer/c ountern overflow interr upt vector is executed. alternatively, tovn can be cleared by writing a logic one to its bit location. 145 7679h?can?08/08 at90can32/64/128 14. 8-bit timer/counter2 with pwm and asynchronous operation timer/counter2 is a general purpose, single channel, 8-bit timer/counter module. the main features are: 14.1 features ? single channel counter ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (pwm) ? frequency generator ? 10-bit clock prescaler ? overflow and compare match interrupt sources (tov2 and ocf2a) ? allows clocking from external 32 khz watch crystal independent of the i/o clock 14.2 overview many register and bit references in this section are written in general form. ? a lower case ?n? replaces the timer/counter number, in this case 2. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt2 for accessing timer/counter2 c ounter value and so on. ? a lower case ?x? replaces the output compare unit channel, in this case a. however, when using the register or bit defines in a program, the precise form must be used, i.e., ocr2a for accessing timer/counter2 output compare channel a value and so on. a simplified block diagram of the 8-bit timer/counter is shown in figure 14-1 . for the actual placement of i/o pins, refer to figure 1-2 on page 5 or figure 1-3 on page 6 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bo ld. the device-specific i/o register and bit locations are listed in the ?8-bit timer/counter register description? on page 157 . 146 7679h?can?08/08 at90can32/64/128 figure 14-1. 8-bit timer/counter2 block diagram the timer/counter (tcnt2) and output compare register (ocr2a) are 8-bit registers. inter- rupt request (shorten as int.req.) signals are al l visible in the timer interrupt flag register (tifr2). all interrupts are individually masked with the timer interrupt mask register (timsk2). tifr2 and timsk2 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or asynchronously clocked from the tosc1/2 pins, as detailed later in this sect ion. the asynchronous operation is controlled by the asynchronous status regist er (assr). the clock select lo gic block controls which clock source the timer/counter uses to increment (or de crement) its value. the timer/counter is inac- tive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t2 ). the double buffered output compare register (ocr2a) is compared with the timer/counter value at all times. the result of the compare can be used by the waveform generator to gener- ate a pwm or variable frequency output on the output compare pin (oc2a). see ?output compare unit? on page 148. for details. the compare match ev ent will also set the compare flag (ocf2a) which can be used to generate an output compare interrupt request. timer/counter data bus = tcntn waveform generation ocnx = 0 control logic = 0xff top bottom count clear direction tovn (int.req.) ocnx (int.req.) synchronization unit ocrnx tccrnx assrn status flags clk i/o clk asy synchronized status flags asynchronous mode select (asn) tosc2 t/c oscillator tosc1 prescaler clk tn clk i/o 147 7679h?can?08/08 at90can32/64/128 14.2.1 definitions the following definitions are used ex tensively throughout the section: 14.3 timer/counter clock sources the timer/counter can be clocked by an internal synchronous or an external asynchronous clock source. the clock so urce is selected by the clock select logic which is controlled by the clock select (cs22:0) bits located in the ti mer/counter control register (tccr2).the clock source clk t2 is by default equal to the mcu clock, clk i/o . when the as2 bit in the assr register is written to logic one, the cl ock source is taken from the ti mer/counter oscilla tor connected to tosc1 and tosc2 or directly from tosc1. for details on asynchronous operation, see ?asyn- chronous status register ? assr? on page 160 . for details on clock so urces and prescaler, see ?timer/counter2 prescaler? on page 163 . 14.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 14-2 shows a block diagram of the coun ter and its surrounding environment. figure 14-2. counter unit block diagram figure 14-3. signal description (internal signals): count increment or decrement tcnt2 by 1. direction selects between increment and decrement. clear clear tcnt2 (set all bits to zero). clk t 2 timer/counter clock. top signalizes that tcnt2 has reached maximum value. bottom signalizes that tcnt2 has reached minimum value (zero). bottom the counter reaches the bottom when it becomes zero (0x00). max the counter reaches its maximum wh en it becomes 0xff (decimal 255). top the counter reaches the to p when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr2a register. the assignment is depen- dent on the mode of operation. data bus tcntn control logic count tovn (int.req.) top bottom direction clear tosc2 t/c oscillator tosc1 prescaler clk i/o clk tn clk tns 148 7679h?can?08/08 at90can32/64/128 depending on the mode of operation used, the co unter is cleared, incremented, or decremented at each timer clock (clk t2 ). clk t2 can be generated from an external or internal clock source, selected by the clock select bits (cs22:0). w hen no clock source is selected (cs22:0 = 0) the timer is stopped. however, the tcnt2 value can be accessed by the cpu, regardless of whether clk t2 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the se tting of the wgm21 and wgm20 bits located in the timer/counter control register (tccr2a). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare output oc2a. for more details about advanced count ing sequences and waveform generation, see ?modes of operation? on page 150 . the timer/counter overflow flag (tov2) is set a ccording to the mode of operation selected by the wgm21:0 bits. tov2 can be us ed for generating a cpu interrupt. 14.5 output compare unit the 8-bit comparator continuously compares tcnt2 with the output compare register (ocr2a). whenever tcnt2 equals ocr2a, the com parator signals a match. a match will set the output compare flag (ocf2a) at the next timer clock cycle. if enabled (ocie2a = 1), the output compare flag generates an output comp are interrupt. the ocf2a flag is automatically cleared when the interrupt is executed. alternativ ely, the ocf2a flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the wgm21:0 bits and compare output mode (com2a1:0) bits. the max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( ?modes of oper- ation? on page 150 ). figure 14-4 shows a block diagram of the output compare unit. figure 14-4. output compare unit, block diagram the ocr2a register is double buffered when us ing any of the pulse wi dth modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering syn chronizes the update of the ocr2a compare ocfnx (int.req.) = (8-bit comparator ) ocrnx ocnx data bus tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 149 7679h?can?08/08 at90can32/64/128 register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr2a register access may seem complex, but this is not case. when the double buffer- ing is enabled, the cpu has access to the ocr2 a buffer register, and if double buffering is disabled the cpu will access the ocr2a directly. 14.5.1 force output compare in non-pwm waveform generation modes, the matc h output of the comparator can be forced by writing a one to the fo rce output compare (foc2a) bit. fo rcing compare match will not set the ocf2a flag or reload/clear the ti mer, but the oc2a pin will be updated as if a real compare match had occurred (the com2a1:0 bits settings define whether the oc2a pin is set, cleared or toggled). 14.5.2 compare match blocking by tcnt2 write all cpu write operations to the tcnt2 register will block any com pare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allo ws ocr2a to be initial- ized to the same value as tcnt2 without trigge ring an interrupt when the timer/counter clock is enabled. 14.5.3 using the output compare unit since writing tcnt2 in any mode of operation will block all comp are matches for one timer clock cycle, there are risks involved when changing tcnt2 when using the output compare channel, independently of whether the time r/counter is running or not. if the value written to tcnt2 equals the ocr2a value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt2 value equal to bottom when the counter is downcounting. the setup of the oc2a should be performed befo re setting the data direc tion register for the port pin to output. the easiest way of setting the oc2a value is to use the force output com- pare (foc2a) strobe bit in normal mode. the oc2a register keeps its value even when changing between waveform generation modes. be aware that the com2a1:0 bits are not double buffered together with the compare value. changing the com2a1:0 bits will take effect immediately. 14.6 compare match output unit the compare output mode (com2a1:0) bits have two functions. the waveform generator uses the com2a1:0 bits for defining the output compare (oc2a) state at the next compare match. also, the com2a1:0 bits control the oc2a pin output source. figure 14-5 shows a sim- plified schematic of the logic affected by the com2a1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control regis- ters (ddr and port) that are affected by the co m2a1:0 bits are shown. when referring to the oc2a state, the reference is for the internal oc2a register, not the oc2a pin. 150 7679h?can?08/08 at90can32/64/128 figure 14-5. compare match output unit, schematic 14.6.1 compare output function the general i/o port function is overridden by the output compare (oc2a) from the waveform generator if either of the com2a1:0 bits are se t. however, the oc2a pin direction (input or out- put) is still controlled by the da ta direction register (ddr) for th e port pin. the data direction register bit for the oc2a pin (ddr_oc2a) must be set as output before the oc2a value is vis- ible on the pin. the port override function is independent of the waveform generation mode. the design of the output compare pin logic allo ws initialization of the oc2a state before the output is enabled. note that some com2a1:0 bit settings are reserved for certain modes of operation. see ?8-bit timer/counter register description? on page 157. 14.6.2 compare output mode and waveform generation the waveform generator uses the com2a1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com2a1 :0 = 0 tells the waveform gene rator that no action on the oc2a register is to be performe d on the next compare match. for compare output actions in the non-pwm modes refer to table 14-2 on page 158 . for fast pwm mode, refer to table 14-3 on page 158 , and for phase correct pwm refer to table 14-4 on page 159 . a change of the com2a1:0 bits st ate will have effect at the first compare match after the bits are written. for non-pwm modes, the action can be fo rced to have immediate effect by using the foc2a strobe bits. 14.7 modes of operation the mode of operation, i.e., t he behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm21:0) and compare output mode (com2a1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. th e com2a1:0 bits control whether the pwm output generated should be inverted or not (i nverted or non-inverted pwm). for non-pwm modes the com2a1:0 bits control whether the output should be set, cleared, or toggled at a compare match ( see ?compare match output unit? on page 149. ). port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data bus focnx clk i/o 151 7679h?can?08/08 at90can32/64/128 for detailed timing information refer to ?timer/counter timing diagrams? on page 155 . 14.7.1 normal mode the simplest mode of operation is the normal mode (wgm21:0 = 0). in this mode the counting direction is always up (incre menting), and no counter clear is performed. the counter simply overruns when it passes its maxi mum 8-bit value (top = 0xff) and then restarts from the bot- tom (0x00). in normal o peration the timer/counter overflow flag (tov2) will be set in the same timer clock cycle as the tcnt2 becomes zero. the tov2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. ho wever, combined with the timer overflow interrupt that automatically clears the tov2 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 14.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm 21:0 = 2), the ocr2a register is used to manipulate the counter resolution . in ctc mode the counter is cleared to zero when the counter value (tcnt2) matches the ocr2a. the ocr2a de fines the top value fo r the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 14-6 . the counter value (tcnt2) increases until a compare match occurs between tcnt2 and o cr2a, and then counter (tcnt2) is cleared. figure 14-6. ctc mode, timing diagram an interrupt can be generated each time the c ounter value reaches the top value by using the ocf2a flag. if the interrupt is enabled, the inte rrupt handler routine can be used for updating the top value. however, changing the top to a va lue close to bottom when the counter is run- ning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr2a is lower than the current value of tcnt2, the counter will miss the compar e match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. tcntn ocnx (toggle) ocnx interrupt flag set 1 4 period 2 3 (comnx1:0 = 1) 152 7679h?can?08/08 at90can32/64/128 for generating a waveform output in ctc mode, t he oc2a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com2a1:0 = 1). the oc2a value will not be visible on the port pin unless the data direction for the pin is set to output. the wavefo rm generated will have a maximum frequency of f oc2a = f clk_i/o /2 when ocr2a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). as for the normal mode of operation, the tov2 flag is set in the same time r clock cycle that the counter counts fr om max to 0x00. 14.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm21:0 = 3) provides a high frequency pwm waveform generation option. the fast pwm di ffers from the other pwm option by its sin- gle-slope operation. the counter counts from bottom to max then restarts from bottom. in non-inverting compare output mode, the output compare (oc2a) is cleared on the compare match between tcnt2 and ocr2a, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that uses dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac app lications. high frequency a llows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the max value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 14-7 . the tcnt2 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt2 slopes represent compare matches between ocr2a and tcnt2. figure 14-7. fast pwm mode, timing diagram f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 153 7679h?can?08/08 at90can32/64/128 the timer/counter overflow flag (tov2) is set each time the counter reac hes max. if the inter- rupt is enabled, the interrupt handler routi ne can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc2a pin. setting the com2a1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com2a1:0 to three (see table 14-3 on page 158 ). the actual oc2a value will only be visible on the port pin if the data direction for the port pin is set as out- put. the pwm waveform is generated by setting (or clearing) the oc2a register at the compare match between ocr2a and tcnt2, and clearing (or setting) the oc2a register at the timer clock cycle the counter is cleared (changes from max to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the fast pwm mode. if t he ocr2a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr2a equal to max will result in a constantly high or low output (depending on the polarity of the out put set by the com2a1:0 bits.) a frequency (with 50% duty cycle) waveform out put in fast pwm mode can be achieved by set- ting oc2a to toggle its logical level on each compare match (com2a1:0 = 1). the waveform generated will have a maximum frequency of f oc2a = f clk_i/o /2 when ocr2a is set to zero. this feature is similar to the oc2a toggle in ctc mo de, except the double buff er feature of the out- put compare unit is enabled in the fast pwm mode. 14.7.4 phase correct pwm mode the phase correct pwm mode (wgm21:0 = 1) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to max and then from m ax to bottom. in non- inverting compare output mode, the output comp are (oc2a) is cleared on the compare match between tcnt2 and ocr2a while upcounting, and set on the compare match while down- counting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the sym- metric feature of the dual-slope pwm modes, t hese modes are preferred for motor control applications. the pwm resolution for the phase correct pwm m ode is fixed to eight bits. in phase correct pwm mode the counter is incremented until the counter value matches m ax. when the counter reaches max, it changes the count direction. the tcnt2 value will be equal to max for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 14-8 . the tcnt2 value is in the timing diagram shown as a histogram for illu strating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt2 slopes represent compare matches between ocr2a and tcnt2. f ocnxpwm f clk_i/o n 256 ? ------------------ = 154 7679h?can?08/08 at90can32/64/128 figure 14-8. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc2a pin. setti ng the com2a1:0 bits to two will pr oduce a non-inverted pwm. an inverted pwm output can be generated by setting the com2a1:0 to three (see table 14-4 on page 159 ). the actual oc2a value will only be visible on the port pi n if the data direction for the port pin is set as output. the pwm waveform is generated by clearing (or setting) the oc2a register at the compare match between ocr2a and tcnt2 when the counter increments, and setting (or clearing) the oc2a register at compare match between ocr2a and tcnt2 when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calcu- lated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the phase correct pwm mo de. if the ocr2a is set equal to bottom, the output will be continuously low an d if set equal to max the output will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. at the very start of period 2 in figure 14-8 on page 154 ocnx has a transition from high to low even though there is no compare match. the poin t of this transition is to guarantee symmetry around bottom. there are two cases that gi ve a transition without compare match. ? ocr2a changes its value from max, like in figure 14-8 on page 154 . when the ocr2a value is max the ocn pin value is the same as the result of a down-counting compare tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? ------------------ = 155 7679h?can?08/08 at90can32/64/128 match. to ensure symmetry around bottom the ocn value at max must correspond to the result of an up-counting compare match. ? the timer starts counting from a value higher than the one in ocr2a, and for that reason misses the compare match and hence the ocn change that would have happened on the way up. 14.8 timer/counter timing diagrams the following figures show t he timer/counter in synchronous mode, and the timer clock (clk t2 ) is therefore shown as a clock enable signal. in asynchronous mode, clk i/o should be replaced by the timer/counter oscillator clock. the figures include informati on on when interrupt flags are set. figure 14-9 contains timing data for basic timer/counter operati on. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 14-9. timer/counter timing diagram, no prescaling figure 14-10 shows the same timing data, but with the prescaler enabled. figure 14-10. timer/counter timing diagram, with prescaler (f clk_i/o /8) figure 14-11 shows the setting of ocf2a in all modes except ctc mode. clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) 156 7679h?can?08/08 at90can32/64/128 figure 14-11. timer/counter timing diagram, setting of ocf2a, with prescaler (f clk_i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 157 7679h?can?08/08 at90can32/64/128 figure 14-12 shows the setting of ocf2a and the clearing of tcnt2 in ctc mode. figure 14-12. timer/counter timing diagram, clear timer on compare match mode, with pres- caler (f clk_i/o /8) 14.9 8-bit timer/counter register description 14.9.1 timer/counter2 cont rol register a? tccr2a ? bit 7 ? foc2a: force output compare a the foc2a bit is only active when the wgm bi ts specify a non-pwm mode. however, for ensur- ing compatibility with future devices, this bit mu st be set to zero when tccr2a is written when operating in pwm mode. when writing a logical one to the foc2a bit, an immediate compare match is forced on the waveform generation unit. the oc2a output is changed according to its com2a1:0 bits setting. note t hat the foc2a bit is implemented as a strobe. therefore it is the value present in the com2a1:0 bits that de termines the effect of the forced compare. a foc2a strobe will not gen erate any interrupt, nor will it cl ear the timer in ctc mode using ocr2a as top. the foc2a bit is always read as zero. ? bit 6, 3 ? wgm21:0: waveform generation mode these bits control the counting sequence of th e counter, the source for the maximum (top) counter value, and what type of waveform gener ation to be used. mode s of operation supported by the timer/counter unit are: normal mode, clear timer on compare match (ctc) mode, and ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 7 6 5 4 3 2 1 0 foc2a wgm20 com2a1 com2a0 wgm21 cs22 cs21 cs20 tccr2a read/write w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 158 7679h?can?08/08 at90can32/64/128 two types of pulse width modulation (pwm) modes. see table 14-1 and ?modes of operation? on page 150 . note: 1. the ctc2 and pwm2 bit definition names are now obsolete. use the wgm21:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. ? bit 5:4 ? com2a1:0: compare match output mode a these bits control the output compare pin (oc2a) behavior. if one or both of the com2a1:0 bits are set, the oc2a output overrides the normal po rt functionality of the i/o pin it is connected to. however, note that the data direction regist er (ddr) bit corresponding to oc2a pin must be set in order to enable the output driver. when oc2a is connected to the pin, the function of the com2a1:0 bits depends on the wgm21:0 bit setting. table 14-2 shows the com2a1:0 bit func tionality when the wgm21:0 bits are set to a normal or ctc mode (non-pwm). table 14-3 shows the com2a1:0 bit functionality when the wgm21:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the se t or clear is done at top. see ?fast pwm mode? on page 152 for more details. table 14-1. waveform generation mode bit description (1) mode wgm21 (ctc2) wgm20 (pwm2) timer/counter mode of operation top update of ocr2a at tov2 flag set on 0 0 0 normal 0xff immediate max 1 0 1 pwm, phase correct 0xff top bottom 2 1 0 ctc ocr2a immediate max 3 1 1 fast pwm 0xff top max table 14-2. compare output mode, non-pwm mode com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 0 1 toggle oc2a on compare match. 1 0 clear oc2a on compare match. 1 1 set oc2a on compare match. table 14-3. compare output mode, fast pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01reserved 10 clear oc2a on compare match. set oc2a at top. 11 set oc2a on compare match. clear oc2a at top. 159 7679h?can?08/08 at90can32/64/128 table 14-4 shows the com21:0 bit functionality when the wgm21:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 153 for more details. ? bit 2:0 ? cs22:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see table 14-5 . 14.9.2 timer/counter2 register ? tcnt2 the timer/counter register gives direct ac cess, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt2 register blocks (removes) the compare match on the following timer clock. modifying t he counter (tcnt2) while the counter is running, introduces a risk of missing a compare match between tcnt2 and the ocr2a register. 14.9.3 output compare register a ? ocr2a table 14-4. compare output mode, phase correct pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01reserved 10 clear oc2a on compare match when up-counting. set oc2a on compare match when downcounting. 11 set oc2a on compare match when up-counting. clear oc2a on compare match when downcounting. table 14-5. clock select bit description cs22 cs21 cs20 description 0 0 0 no clock source (timer/counter stopped). 001clk t2s /(no prescaling) 010clk t2s /8 (from prescaler) 011clk t2s /32 (from prescaler) 100clk t2s /64 (from prescaler) 101clk t2s /128 (from prescaler) 110clk t 2 s /256 (from prescaler) 111clk t 2 s /1024 (from prescaler) bit 76543210 tcnt2[7:0] tcnt2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr2a[7:0] ocr2a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 160 7679h?can?08/08 at90can32/64/128 the output compare register a contains an 8-bi t value that is conti nuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2a pin. 14.10 asynchronous operation of the timer/counter2 14.10.1 asynchronous status register ? assr ? bit 7..5 ? reserved bits these bits are reserv ed for future use. ? bit 4 ? exclk: enable external clock input when exclk is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on timer oscillator 1 (tosc1) pin instead of a 32 khz crystal. writing to exclk should be done before asynchronous operation is selected. note that the crystal oscilla tor will only run when this bit is zero. ? bit 3 ? as2: asynchronous timer/counter2 when as2 is written to zero , timer/counter2 is clocked from the i/o clock, clk i/o and the crystal oscillator connected to the timer/ counter2 oscillator (tosc) does nor run. when as2 is written to one, timer/counter2 is clocked from a crystal oscillator connected to the timer/counter2 oscillator (tosc) or from external cl ock on tosc1 depending on exclk setting. when the value of as2 is changed, the contents of t cnt2, ocr2a, and tccr2a might be corrupted. ? bit 2 ? tcn2ub: timer/counter2 update busy when timer/counter2 operates asynchronously and tcnt2 is written, this bit becomes set. when tcnt2 has been updated from the temporary storage register, this bit is cleared by hard- ware. a logical zero in this bit indicates that tcnt2 is ready to be updated with a new value. ? bit 1 ? ocr2ub: output co mpare register2 update busy when timer/counter2 operates asynchronously and ocr2a is written, th is bit becomes set. when ocr2a has been updated from the temporary storage register, this bit is cleared by hard- ware. a logical zero in this bit indicates that ocr2a is ready to be updated with a new value. ? bit 0 ? tcr2ub: timer/counter control register2 update busy when timer/counter2 operates asynchronously and tccr2a is wr itten, this bit becomes set. when tccr2a has been updated from the tempor ary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2a is ready to be updated with a new value. if a write is performed to any of the three timer/ counter2 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. the mechanisms for reading tcnt2, ocr2a, and tccr2a are different. when reading tcnt2, the actual timer value is read. when reading ocr2a or tccr2a, the value in the tem- porary storage register is read. bit 765 4 3 2 1 0 ? ? ? exclk as2 tcn2ub ocr2ub tcr2ub assr read/write r r r r/w r/w r r r initial value 0 0 0 0 0 0 0 0 161 7679h?can?08/08 at90can32/64/128 14.10.2 asynchronous operation of timer/counter2 when timer/counter2 operates asynchronously, some considerations must be taken. ? warning: when switching between asynch ronous and synchronous clocking of timer/counter2, the timer r egisters tcnt2, ocr2a, and tccr2a might be corrupted. a safe procedure for switching clock source is: a. disable the timer/counter2 interrupts by clearing ocie2a and toie2. b. select clock source by settin g as2 and exclk as appropriate. c. write new values to t cnt2, ocr2a, and tccr2a. d. to switch to asynchronous operation: wait for tcn2ub, ocr2ub, and tcr2ub. e. clear the timer/coun ter2 interrupt flags. f. enable interrupts, if needed. ? the oscillator is optimized for use with a 32.768 khz watch crystal. the cpu main clock frequency must be more than four times the oscillator or external clock frequency. ? when writing to one of the registers tcnt2, o cr2a, or tccr2a, the value is transferred to a temporary register, and latched after two po sitive edges on tosc1. the user should not write a new value before the contents of the temporary register have been transferred to its destination. each of the three mentioned regi sters have their individual temporary register, which means that e.g. writing to tcnt2 does not disturb an ocr2a write in progress. to detect that a transfer to the destination regi ster has taken place, the asynchronous status register ? assr has been implemented. ? when entering power-save or extended stan dby mode after having written to tcnt2, ocr2a, or tccr2a, the user must wait until the writte n register has be en updated if timer/counter2 is used to wake up the device. othe rwise, the mcu will enter sleep mode before the changes are effective. this is pa rticularly important if the output compare2 interrupt is used to wake up the device, since the output compare function is disabled during writing to ocr2a or tcnt2. if the write cycl e is not finished, and the mcu enters sleep mode before the ocr2ub bit re turns to zero, the device will never receive a compare match interrupt, and the mcu will not wake up. ? if timer/counter2 is used to wake the device up from power-save or extended standby mode, precautions must be taken if the user wants to re-enter one of these modes: the interrupt logic needs one tosc1 cycle to be reset. if the time between wake-up and re- entering sleep mode is less than one tosc1 cycle, the interrupt will not occur, and the device will fail to wake up. if the user is in do ubt whether the time be fore re-entering power- save mode is sufficient, the following algorithm can be used to ensure that one tosc1 cycle has elapsed: a. write a value to tccr2a, tcnt2, or ocr2a. b. wait until the correspond ing update busy flag in assr returns to zero. c. enter power-save or a dc noise reduction mode. ? when the asynchronous operation is selected, the 32.768 khz oscillator for timer/counter2 is always running, except in power-down and standby modes. after a power-up reset or wake-up from power-down or standby mode, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. the user is advised to wait for at least one second before using timer/counter2 after power-up or wake-up from power-down or standby mode. the contents of all timer/coun ter2 registers must be considered lost after a wake-up from power-down or standby mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use or a clock signal is applied to the tosc1 pin. 162 7679h?can?08/08 at90can32/64/128 ? description of wake up from power-save mode when the timer is clocked asynchronously: when the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always adv anced by at least one before the processor can read the counter value. after wake-up, the mcu is halted for four cycles, it executes the interrupt routine, and resumes executio n from the instruction following sleep. ? reading of the tcnt2 register shortly after wake-up from power-save may give an incorrect result. since tcnt2 is clocked on the asynchro nous tosc clock, reading tcnt2 must be done through a register synchronized to the internal i/o clock domain. synchronization takes place for every rising tosc1 edge. when waking up from power-save mode, and the i/o clock (clk i/o ) again becomes active, tcnt2 will read as the previous value (before entering sleep) until the next rising tosc1 edge. the phas e of the tosc clock after waking up from power-save mode is essentially unpredictable , as it depends on the wake-up time. the recommended procedure for reading tcnt2 is thus as follows: a. write any value to either of the registers ocr2a or tccr2a. b. wait for the corresponding update busy flag to be cleared. c. read tcnt2. ? during asynchronous operation, the synchr onization of the interrupt flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. the timer is therefore advanced by at least one before the processor ca n read the timer value causing the setting of the interrupt flag. the output compare pin is changed on the timer clock and is not synchronized to the processor clock. 14.10.3 timer/counter2 interrupt mask register ? timsk2 ? bit 7..2 ? reserved bits these bits are reserv ed for future use. ? bit 1 ? ocie2a: timer/counter2 output compare match a interrupt enable when the ocie2a bit is written to one and the i- bit in the status register is set (one), the timer/counter2 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter2 occurs , i.e., when the ocf2a bit is set in the timer/counter2 interrupt flag register ? tifr2. ? bit 0 ? toie2: timer/counter2 overflow interrupt enable when the toie2 bit is written to one and the i- bit in the status register is set (one), the timer/counter2 overflow interr upt is enabled. the corresponding interrupt is executed if an overflow in timer/counter2 occurs, i.e., when the tov2 bit is set in the timer/counter2 interrupt flag register ? tifr2. 14.10.4 timer/counter2 interrupt flag register ? tifr2 bit 76543210 ??????ocie2atoie2timsk2 read/write r r r r r r r/w r/w initial value00000000 bit 76543210 ??????ocf2atov2tifr2 read/write r r r r r r r/w r/w initial value00000000 163 7679h?can?08/08 at90can32/64/128 ? bit 7..2 ? reserved bits these bits are reserv ed for future use. ? bit 1 ? ocf2a: output compare flag 2 a the ocf2a bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2a ? output compare register2. ocf2a is cleared by hardware when executing the corresponding interrupt handling vector. alter natively, ocf2a is clear ed by writing a logic one to the flag. when the i-bit in sreg, ocie2 (timer/counter2 compare match interrupt enable), and ocf2a are set (one), the timer/co unter2 compare match interrupt is executed. ? bit 0 ? tov2: timer/counter2 overflow flag the tov2 bit is set (one) when an overflow occu rs in timer/counter2. to v2 is cleared by hard- ware when executing the corresponding interrupt handling vector. alternatively, tov2 is cleared by writing a logic one to the flag. when the sreg i-bit, toie2a (timer/counter2 overflow inter- rupt enable), and tov2 are set (one), the timer/ counter2 overflow interrupt is executed. in pwm mode, this bit is set when timer/counter2 changes counting direction at 0x00. 14.11 timer/counter2 prescaler figure 14-13. prescaler for timer/counter2 the clock source for timer/counter2 is named clk t2s . clk t2s is by default connected to the main system i/o clock clk io . by setting the as2 bit in assr, timer/counter2 is asynchronously clocked from the tosc oscillator or tosc1 pin. this enables use of timer/counter2 as a real time counter (rtc). a crystal can then be connected between the to sc1 and tosc2 pins to serve as an indepen- dent clock source for timer/counter2. the os cillator is optimized for use with a 32.768 khz crystal. setting as2 and resetting exc lk enables the tosc oscillator. 10-bit t/c prescaler timer/counter2 clock source clk i/o clk t2s as2 cs20 cs21 cs22 clk t2s /8 clk t2s /64 clk t2s /128 clk t2s /1024 clk t2s /256 clk t2s /32 0 psr2 clear clk t2 0 1 tosc2 exclk 0 1 as2 exclk 32 khz oscillator enable tosc1 164 7679h?can?08/08 at90can32/64/128 figure 14-14. timer/counter2 crysta l oscillator connections a external clock can also be used using tosc 1 as input. setting as2 and exclk enables this configuration. figure 14-15. timer/counter2 external clock connections for timer/counter2, t he possible prescaled selections are: clk t2s /8, clk t2s /32, clk t2s /64, clk t2s /128, clk t2s /256, and clk t2s /1024. additionally, clk t2s as well as 0 (stop) may be selected. setting the psr2 bit in gtccr resets the prescaler. this allows the user to operate with a pre- dictable prescaler. 14.11.1 general timer/counter control register ? gtccr ? bit 1 ? psr2: prescaler reset timer/counter2 when this bit is one, the time r/counter2 prescaler will be rese t. this bit is normally cleared immediately by hardware. if the bit is written wh en timer/counter2 is operating in asynchronous mode, the bit will remain one until the presca ler has been reset. the bit will not be cleared by hardware if the tsm bit is set. refer to the description of the ?bit 7 ? tsm: timer/counter syn- chronization mode? on page 98 for a description of the timer/ counter synchronization mode. tosc2 tosc1 gnd 12 - 22 pf 12 - 22 pf 32.768 khz tosc2 tosc1 nc external clock signal bit 7 6 5 4 3 2 1 0 tsm ? ? ? ? ? psr2 psr310 gtccr read/write r/w r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 165 7679h?can?08/08 at90can32/64/128 15. output compare modulator - ocm 15.1 overview many register and bit references in this section are written in general form. ? a lower case ?n? replaces the timer/counter nu mber, in this case 0 and 1. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 c ounter value and so on. ? a lower case ?x? replaces the output compare unit channel, in this case a or c. however, when using the register or bit defines in a program, the precise form must be used, i.e., ocr0a for accessing timer/counter0 output compare channel a value and so on. the output compare modulator (ocm) allows generation of waveforms modulated with a carrier frequency. the modulator uses the outputs from the output compare unit c of the 16-bit timer/counter1 and the output compare unit of the 8-bit timer/counter0. for more details about these timer/counters see ?16-bit timer/counter (timer/counter1 and timer/counter3)? on page 113 and ?8-bit timer/counter0 with pwm? on page 99 . figure 15-1. output compare modulator, block diagram when the modulator is enabled, the two output compare channels are modulated together as shown in the block diagram ( figure 15-1 ). 15.2 description the output compare unit 1c and output compare unit 0a shares the pb7 port pin for output. the outputs of the output compare units (oc1c and oc0a) overrides the normal portb7 register when one of them is enabled (i.e., when comnx1:0 is not equal to zero). when both oc1c and oc0a are enabled at the same ti me, the modulator is automatically enabled. when the modulator is enabled the type of modul ation (logical and or or) can be selected by the portb7 register. note that the ddrb7 controls the direction of the port independent of the comnx1:0 bit setting. the functional equivalent schemati c of the modulator is shown on figure 15-2 . the schematic includes part of the timer/counter units and the port b pin 7 output driver circuit. oc1c pin oc0a / oc1c / pb7 timer/counter 1 timer/counter 0 oc0a 166 7679h?can?08/08 at90can32/64/128 figure 15-2. output compare modulator, schematic 15.2.1 timing example figure 15-3 illustrates the modulator in ac tion. in this example the ti mer/counter1 is set to oper- ate in fast pwm mode (non-inverted) and time r/counter0 uses ctc wa veform mode with toggle compare output mode (comnx1:0 = 1). figure 15-3. output compare modulator, timing diagram in this example, timer/counter0 provides the carrier, while the modulating signal is generated by the output compare unit c of the timer/counter1. portb7 ddrb7 dq dq pin databus com0a1 com0a0 oc0a / oc1c / pb7 com1c1 com1c0 modulator 1 0 oc1c dq oc0a dq (from t/c1 waveform generator) (from t/c0 waveform generator) 0 1 vcc 1 2 oc0a (ctc mode) oc1c (fpwm mode) pb7 (portb7 = 0) pb7 (portb7 = 1) (period) 3 clk i/o 167 7679h?can?08/08 at90can32/64/128 15.2.2 resolution of the pwm signal the resolution of the pwm signal (oc1c) is re duced by the modulation. the reduction factor is equal to the number of system clock cycles of one period of the carrier (oc0a). in this example the resolution is reduced by a factor of two. the reason for the reduction is illustrated in figure 15-3 at the second and third period of the pb7 output when portb7 equals zero. the period 2 high time is one cycle longer than the period 3 high time, but the result on the pb7 output is equal in both periods. 168 7679h?can?08/08 at90can32/64/128 16. serial peripheral interface ? spi the serial peripheral interface (spi) allows hi gh-speed synchronous data transfer between the at90can32/64/128 and peripheral devices or between several avr devices. the at90can32/64/128 spi includes the following features: 16.1 features ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode figure 16-1. spi block diagram (1) note: 1. refer to figure 1-2 on page 5 or figure 1-3 on page 6 , and table 9-6 on page 76 for spi pin placement. spi2x spi2x divider /2/4/8/16/32/64/128 clk io 169 7679h?can?08/08 at90can32/64/128 the interconnection between master an d slave cpus with spi is shown in figure 16-2 . the sys- tem consists of two shift registers, and a master clock generator. the spi master initiates the communication cycle when pu lling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to in terchange data. data is always shifted from mas- ter to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after ea ch data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before commu nication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte, the spi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt en able bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may conti nue to place new data to be sent into spdr before reading the incoming data. the last incomi ng byte will be kept in the buffer register for later use. figure 16-2. spi master-slave interconnection the system is single buffered in the transmit direction and double buffered in the receive direc- tion. this means that bytes to be transmitted ca nnot be written to the spi data register before the entire shift cycle is complet ed. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. oth- erwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming signal of the sck pin. to ensure correct sampling of the clock signal, the minimum low and high period should be: ? low period: longer than 2 cpu clock cycles, ? high period: longer than 2 cpu clock cycles. shift enable 170 7679h?can?08/08 at90can32/64/128 when the spi is enabled, the data di rection of the mosi, miso, sck, and ss pins is overridden according to table 16-1 . for more details on automatic port overrides, refer to ?alternate port functions? on page 71 . note: 1. see ?alternate functions of port b? on page 76 for a detailed description of how to define the direction of the user defined spi pins. table 16-1. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input 171 7679h?can?08/08 at90can32/64/128 the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples must be replaced by th e actual data direction register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actual data direction bits for these pins. e.g. if mosi is placed on pin pb2, replace dd_mosi with ddb2 and ddr_spi with ddrb. note: 1. the example code assumes that the part specific header file is included. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 174 7679h?can?08/08 at90can32/64/128 and spif in spsr will become set. the user will th en have to set mstr to re-enable spi mas- ter mode. ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when idle. when cpol is written to zero, sck is low when idle. refer to figure 16-3 and figure 16-4 for an example. the cpol functionality is sum- marized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determ ine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 16-3 and figure 16-4 for an example. the cpol functionality is summarized below: ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the dev ice configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the clk io frequency f clkio is shown in the following table: table 16-2. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 16-3. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample table 16-4. relationship between sck an d the oscillator frequency spi2x spr1 spr0 sck frequency 000 f clkio / 4 001 f clkio / 16 010 f clkio / 64 011 f clkio / 128 100 f clkio / 2 101 f clkio / 8 110 f clkio / 32 111 f clkio / 64 175 7679h?can?08/08 at90can32/64/128 16.2.4 spi status register ? spsr ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif fl ag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is dr iven low when the spi is in master mode, this will also set the spif flag. spif is cleared by hardware when executing the corresponding interrupt handling vector. alternativel y, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by firs t reading the spi status register with wcol set, and then accessing the spi data register. ? bit 5..1 ? res: reserved bits these bits are reserved bits in the at90 can32/64/128 and will a lways read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logi c one the spi speed (sck freque ncy) will be doubled when the spi is in master mode (see table 16-4 ). this means that the mini mum sck period will be two cpu clock periods. when the spi is configured as sl ave, the spi is only guaranteed to work at f clkio /4 or lower. the spi interface on the at90can32/64/128 is also used for program memory and eeprom downloading or uploading. see ?spi serial programming overview? on page 348 for serial pro- gramming and verification. 16.2.5 spi data register ? spdr ? bits 7:0 - spd7:0: spi data the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the regist er initiates data transmis sion. reading the regis- ter causes the shift register receive buffer to be read. 16.3 data modes there are four combinations of sck phase and po larity with respect to serial data, which are determined by control bits cpha and cpol. the spi data transfer formats are shown in figure 16-3 and figure 16-4 . data bits are shifted out and latch ed in on opposite edges of the sck sig- bit 76543210 spifwcol?????spi2xspsr read/write r r r r r r r r/w initial value00000000 bit 76543210 spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x undefined 176 7679h?can?08/08 at90can32/64/128 nal, ensuring sufficient time for data signals to st abilize. this is clearly seen by summarizing table 16-2 and table 16-3 , as done below: figure 16-3. spi transfer format with cpha = 0 figure 16-4. spi transfer format with cpha = 1 table 16-5. cpol functionality leading edge trailing edge spi mode cpol=0, cpha=0 sample (rising) setup (falling) 0 cpol=0, cpha=1 setup (rising) sample (falling) 1 cpol=1, cpha=0 sample (falling) setup (rising) 2 cpol=1, cpha=1 setup (falling) sample (rising) 3 bit 1 bit 6 lsb msb sck (cpol = 0) mode 0 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 2 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 msb first (dord = 0) lsb first (dord = 1) sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb first (dord = 0) lsb first (dord = 1) 177 7679h?can?08/08 at90can32/64/128 17. usart (usart0 and usart1) the universal synchronous and asynchronous serial receiver and transmitter (usart) is a highly flexible serial communicati on device. the main features are: 17.1 features ? full duplex operation (independent serial receive and transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high resolution baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? odd or even parity generation and parity check supported by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bit detection and digital low pass filter ? three separate interrupts on tx complete , tx data register empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode 17.2 overview many registers and bit references in this section are written in general form. ? a lower case ?n? replaces the usart number, in this case 0 or 1. however, when using the register or bit defines in a program, the prec ise form must be used, i.e., udr0 for accessing usart0 i/o data value and so on. 17.3 dual usart the at90can32/64/128 has two usart?s, usar t0 and usart1. the functionality for both usart?s is described below. usart0 and usar t1 have different i/o registers as shown in ?register summary? on page 405 . a simplified block diagram of the usartn transmitter is shown in figure 17-1 . cpu accessible i/o registers and i/o pins are shown in bold. 178 7679h?can?08/08 at90can32/64/128 figure 17-1. usartn block diagram (1) note: 1. refer to figure 1-2 on page 5 or figure 1-3 on page 6 , table 9-15 on page 83 , and table 9-10 on page 79 for usartn pin placement. the dashed boxes in the block diagram separate the three main parts of the usartn (listed from the top): clock generator, transmitter and receiver. control registers are shared by all units. the clock generation logic consists of sy nchronization logic for external clock input used by synchronous slave operation, and the baud ra te generator. the xckn (transfer clock) pin is only used by synchronous transfer mode. the transmi tter consists of a single write buffer, a serial shift register, parity generator and cont rol logic for handling different serial frame for- mats. the write buffer allows a continuous transf er of data without any delay between frames. the receiver is the most complex part of the u sartn module due to its clock and data recovery units. the recovery units are used for asynchronous data reception. in addition to the recovery units, the receiver includes a parity checker, control logic, a shift register and a two level receive buffer (udrn). the receiver supports the same frame formats as the transmitter, and can detect frame error, data overrun and parity errors. parity generator ubrrn[h:l] udr n (transmit) ucsran ucsrbn ucsrcn baud rate generator transmit shift register receive shift register rxdn txdn pin control udrn (receive) pin control xckn data recovery clock recovery pin control tx control rx control parity checker data bus clkio sync logic clock generator transmitter receiver 179 7679h?can?08/08 at90can32/64/128 17.4 clock generation the clock generation logic generates the base clock for the transmitter and receiver. the usartn supports four modes of clock opera tion: normal asynchronous, double speed asyn- chronous, master synchronous and slave synchronous mode. the umseln bit in usartn control and status register c (ucsrnc) selects between asynchronous and synchronous operation. double speed (asynchronous mode only) is controlled by the u2xn found in the ucsrna register. when using synchronous mode (umseln = 1), the data direction register for the xckn pin (ddr_xckn) c ontrols whether the clock source is internal (master mode) or external (slave mode). the xckn pin is only active when using synchronous mode. figure 17-2 shows a block diagram of the clock generation logic. figure 17-2. usartn clock generation logic, block diagram signal description: txn clk transmitter clock (internal signal). rxn clk receiver base clock (internal signal). xn cki input from xck pin (internal sign al). used for synchronous slave operation. xn cko clock output to xck pin (internal si gnal). used for synchronous master operation. f clk io system i/o clock frequency. 17.4.1 internal clock genera tion ? baud rate generator internal clock generation is used for the as ynchronous and the synchronous master modes of operation. the description in this section refers to figure 17-2 . the usartn baud rate register (ubrrn) and th e down-counter connected to it function as a programmable prescaler or baud rate generator. the down-counter, running at system clock ( f clk io ), is loaded with the ubrrn value each time the counter has counted down to zero or when the ubrrnl register is written. a clock is generated each time the counter reaches zero. this clock is the baud rate generator clock output (= f clk io /(ubrrn+1)). the tr ansmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. the baud rate generator output is used directly by the receiver?s cloc k and data recovery unit s. however, the recovery prescaling down-counter /2 ubrrn /4 /2 sync register clk xckn pin txn clk u2xn umseln ddr_xckn 0 1 0 1 xn cki xn cko ddr_xckn rxn clk 0 1 1 0 edge detector ucpoln io ubrrn+1 f clk io 180 7679h?can?08/08 at90can32/64/128 units use a state machine that uses 2, 8 or 16 st ates depending on mode set by the state of the umseln, u2xn and ddr_xckn bits. table 17-1 contains equations for calculating the baud rate (in bits per second) and for calculat- ing the ubrrn value for each mode of operation using an internally generated clock source. note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps). f clk io system i/o clock frequency. ubrrn contents of the ubrrnh and ubrrnl registers, (0-4095). some examples of ubrrn values for some system clock frequencies are found in table 17-9 (see page 200 ). 17.4.2 double speed operation (u2x) the transfer rate can be doubled by setting the u2 xn bit in ucsrna. setting this bit only has effect for the asynchronous operation. set this bit to zero when using synchronous operation. setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. note however that the receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud ra te setting and system clock are required when this mode is used. for the transmitter, there are no downsides. 17.4.3 external clock external clocking is used by the synchronous sl ave modes of operation. the description in this section refers to figure 17-2 for details. external clock input from the xckn pin is sample d by a synchronization register to minimize the chance of meta-stability. the output from the synchronizati on register must then pass through an edge detector before it can be used by the transmitter and receiver. this process intro- duces a two cpu clock period delay and therefore the maximum external xckn clock frequency is limited by the following equation: table 17-1. equations for calculating baud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrrn value asynchronous normal mode (u2xn = 0) asynchronous double speed mode (u2xn = 1) synchronous master mode baud f clkio 16 ubrr n 1 + () ----------------------------------------- - = ubrr n f clkio 16 baud ----------------------- - 1 ? = baud f clkio 8 ubrr n 1 + () -------------------------------------- - = ubrr n f clkio 8 baud -------------------- 1 ? = baud f clkio 2 ubrr n 1 + () -------------------------------------- - = ubrr n f clkio 2 baud -------------------- 1 ? = f xckn f clkio 4 --------------- - < 181 7679h?can?08/08 at90can32/64/128 note that f clk io depends on the stability of the system clock source. it is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 17.4.4 synchronous clock operation when synchronous mode is used (umseln = 1), th e xckn pin will be used as either clock input (slave) or clock output (master). the depen dency between the clock edges and data sampling or data change is the same. the basic principle is that data input (on rxdn) is sampled at the opposite xckn clock edge of the edge the data output (txdn) is changed. figure 17-3. synchronous mode xckn timing. the ucpoln bit ucrsnc selects which xckn clock edge is used for data sampling and which is used for data change. as figure 17-3 shows, when ucpoln is ze ro the data will be changed at rising xckn edge and sampled at falling xc kn edge. if ucpoln is set, the data will be changed at falling xckn edge and sampled at rising xckn edge. 17.5 serial frame a serial frame is defined to be one character of da ta bits with synchronizat ion bits (start and stop bits), and optionally a parity bit for error checking. 17.5.1 frame formats the usartn accepts all 30 combinations of the following as valid frame formats: ? 1 start bit ? 5, 6, 7, 8, or 9 data bits ? no, even or odd parity bit ? 1 or 2 stop bits a frame starts with the start bit followed by the le ast significant data bit. then the next data bits, up to a total of nine, are succeeding, ending with t he most significant bit. if enabled, the parity bit is inserted after the data bits, before the stop bits . when a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. figure 17-4 illustrates the possible combinations of th e frame formats. bits inside brackets are optional. rxdn / txdn xckn rxdn / txdn xckn ucpoln = 0 ucpoln = 1 sample sample 182 7679h?can?08/08 at90can32/64/128 figure 17-4. frame formats st start bit, always low. (n) data bits (0 to 8). p parity bit. can be odd or even. sp stop bit, always high. idle no transfers on the communication line (rxdn or txdn). an idle line must be high. the frame format used by the usartn is set by the ucszn2:0, upmn1:0 and usbsn bits in ucsrnb and ucsrnc. the receiver and transmitte r use the same setting. note that changing the setting of any of these bits will corrupt a ll ongoing communication for both the receiver and transmitter. the usartn character size (ucszn2:0) bits select the number of data bits in the frame. the usartn parity mode (upmn1:0 ) bits enable and set the type of parity bit. the selection between one or two stop bits is done by the u sartn stop bit select (u sbsn) bit. the receiver ignores the second stop bit. an fen (frame error) will therefore on ly be detected in the cases where the first stop bit is zero. 17.5.2 parity bit calculation the parity bit is calculated by do ing an exclusive-or of all the data bits. if odd parity is used, the result of the exclusive or is inverted. the re lation between the parity bit and data bits is as follows: p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is locate d between the last data bit and first stop bit of a serial frame. 17.6 usart initialization the usartn has to be initialized before any co mmunication can take place. the initialization process normally consists of se tting the baud rate, setting frame format and enabling the trans- mitter or the receiver depending on the usage. fo r interrupt driven usartn operation, the global interrupt flag should be cleared (and interrupts globally disabled) when doing the initialization. before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxcn flag can be used to 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame p even d n 1 ? d 3 d 2 d 1 d 0 0 p odd d n 1 ? d 3 d 2 d 1 d 0 1 = = 183 7679h?can?08/08 at90can32/64/128 check that there are no unread data in the receive buffer. note that the txcn flag must be cleared before each transmission (before udrn is written) if it is used for this purpose. the following simple usart0 init ialization code examples show one assembly and one c func- tion that are equal in functionality. the exampl es assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. note: 1. the example code assumes that the part specific header file is included. more advanced initialization rout ines can be made that include frame format as parameters, dis- able interrupts and so on. however, many appl ications use a fixed setting of the baud and control registers, and for these ty pes of applications the initializat ion code can be placed directly in the main routine, or be combined with initialization code for other i/o modules. 17.7 data transmission ? usart transmitter the usartn transmitter is enabled by settin g the transmit enable (txenn) bit in the ucsrnb register. when the transmitter is enabled, the nor mal port operation of the txdn pin is overrid- den by the usartn and given th e function as the transmitter?s serial output. the baud rate, mode of operation and frame format must be set up once before doing any transmissions. if syn- assembly code example (1) usart0_init: ; set baud rate sts ubrr0h, r17 sts ubrr0l, r16 ; set frame format: 8data, no parity & 2 stop bits ldi r16, (0< 187 7679h?can?08/08 at90can32/64/128 the following code example shows a simple usar t0 receive function bas ed on polling of the receive complete (rxc0) flag. when using frames with less than eight bits the most significant bits of the data read from the udr0 will be ma sked to zero. the usart0 has to be initialized before the function can be used. note: 1. the example code assumes that the part specific header file is included. the function simply waits for data to be present in the receive buffer by checking the rxc0 flag, before reading the buffer and returning the value. 17.8.2 receiving frames with 9 data bits if 9-bit characters are used (ucszn=7) the ninth bit must be read from the rxb8n bit in ucs- rnb before reading the low bits from the udrn. this rule applies to the fe n, dorn and upen status flags as well. read st atus from ucsrna, then data from udrn. reading the udrn i/o location will change the state of the receive bu ffer fifo and consequ ently the txb8n, fen, dorn and upen bits, which all ar e stored in the fifo, will change. assembly code example (1) usart0_receive: ; wait for data to be received lds r18, ucsr0a sbrs r18, rxc0 rjmp usart0_receive ; get and return received data from buffer lds r16, udr0 ret c code example (1) unsigned char usart0_receive ( void ) { /* wait for data to be received */ while ( ! (ucsr0a & (1< 189 7679h?can?08/08 at90can32/64/128 17.8.3 receive complete flag and interrupt the usartn receiver has one flag that indicates the receiver state. the receive complete (rxcn) flag indicates if there are unread data present in the receive buffer. this flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled (rxenn = 0), the receive buffer will be flushed and cons equently the rxcn bit will become zero. when the receive complete interrupt enabl e (rxcien) in ucsrnb is set, the usartn receive complete interrupt will be executed as long as the rxcn flag is set (p rovided that glo- bal interrupts are enabled). when interrupt-drive n data reception is used, the receive complete routine must read the received data from udrn in order to clear the rxcn flag, otherwise a new interrupt will occur once the in terrupt routin e terminates. 17.8.4 receiver error flags the usartn receiver has three error flags: frame error (fen), data overrun (dorn) and parity error (upen). all can be accessed by reading ucsrna. common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. due to the buffering of the error flags, the ucsrna must be read before the receive buffer (udrn), since reading the udrn i/o lo cation changes the buffe r read location. another equality for the error flags is that they can not be altered by software doing a write to the flag location. however, all flags must be set to zero when the ucsrna is written for upward compat- ibility of future usart implemen tations. none of the error fl ags can generate interrupts. the frame error (fen) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. the fen flag is zero when the stop bit was correctly read (as one), and the fen flag will be one when the stop bit wa s incorrect (zero). this flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. the fen flag is not affected by the setting of the usbsn bit in ucsrnc since the receiver ignores all, except for the first, stop bits. for compatibility with future devices, always set this bit to zero when writ- ing to ucsrna. the data overrun (dorn) flag indicates data loss due to a receiver buffer full condition. a data overrun occurs when the receive buf fer is full (two characters), it is a new character waiting in the receive shift register, and a new start bit is detected. if th e dorn flag is set there was one or more serial frame lost between the frame last read from udrn, and the next frame read from udrn. for compatibility with future devices, alwa ys write this bit to zero when writing to ucs- rna. the dorn flag is cleared when the frame received was successfully moved from the shift register to the receive buffer. the parity error (upen) flag indicates that the next frame in the receive buffer had a parity error when received. if parity check is not enabled the upen bit will always be read zero. for compatibility with future devices, always set this bit to zero when writing to ucsrna. for more details see ?parity bit calculation? on page 182 and ?parity checker? on page 189 . 17.8.5 parity checker the parity checker is active when the high usartn parity mode (upmn1) bit is set. type of parity check to be performed (odd or even) is selected by the upmn0 bit. when enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. the result of the check is stored in the receive buffer together with the received data and stop bits. the parity error (upen) flag can then be read by software to check if the frame had a parity error. 190 7679h?can?08/08 at90can32/64/128 the upen bit is set if the nex t character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. 17.8.6 disabling the receiver in contrast to the transmitter, disabling of the receiver will be immediate. data from ongoing receptions will therefore be lost. when disabled (i .e., the rxenn is set to zero) the receiver will no longer override the normal function of the rxdn port pin. the receiver buffer fifo will be flushed when the receiver is disabled. remaining data in the buffer will be lost 17.8.7 flushing the receive buffer the receiver buffer fifo will be fl ushed when the receiver is disa bled, i.e., the buffer will be emptied of its contents. unread data will be los t. if the buffer has to be flushed during normal operation, due to for instance an error condition, read the udrn i/o location until the rxcn flag is cleared. the following code example shows how to flush the receive buffer. note: 1. the example code assumes that the part specific header file is included. 17.9 asynchronous data reception the usartn includes a clock recovery and a data recovery unit for handling asynchronous data reception. the clock recovery l ogic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the rxdn pin. the data recovery logic sam- ples and low pass filters each incoming bit, ther eby improving the noise immunity of the receiver. the asynchronous reception operational range depends on the accuracy of the inter- nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 17.9.1 asynchronous clock recovery the clock recovery logic synchronizes internal clock to the incoming serial frames. figure 17-5 illustrates the sampling process of th e start bit of an incoming frame. the sample rate is 16 times the baud rate for normal mode, and eight times the baud rate for double speed mode. the hor- assembly code example (1) usart0_flush: lds r16, ucsr0a sbrs r16, rxc0 ret lds r16, udr0 rjmp usart0_flush c code example (1) void usart0_flush ( void ) { unsigned char dummy; while (ucsr0a & (1< 192 7679h?can?08/08 at90can32/64/128 figure 17-7 shows the sampling of the stop bit and the ea rliest possible beginning of the start bit of the next frame. figure 17-7. stop bit sampling and ne xt start bit sampling the same majority voting is done to the stop bit as done for the other bits in the frame. if the stop bit is registered to have a logic 0 value, the frame error (fen ) flag will be set. a new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority vo ting. for normal speed mode, the first low level sample can be at point marked (a) in figure 17-7 . for double speed mode the firs t low level must be delayed to (b). (c) marks a stop bit of full length. the ear ly start bit detection influences the operational range of the receiver. 17.9.3 asynchronous operational range the operational range of the receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. if the transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see table 17-2 ) base frequency, the receiver will not be abl e to synchronize the frames to the start bit. the following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. d sum of character size and parity size (d = 5 to 10 bit) s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. r fas t is the ratio of the fastest incoming data ra te that can be accepted in relation to the receiver baud rate. table 17-2 and table 17-3 list the maximum receiver baud rate error that can be tolerated. note that normal speed mode has higher toleration of baud rate variations. 1234567 8 9 10 0/1 0/1 0/1 stop 1 123 4 5 6 0/1 rxdn sample (u2xn = 0) sample (u2xn = 1) (a) (b) (c) r slow d 1 + () s s 1 ? ds ? s f ++ ------------------------------------------ - = r fast d 2 + () s d 1 + () ss m + ----------------------------------- = 193 7679h?can?08/08 at90can32/64/128 the recommendations of the maximum receiver baud rate error was made under the assump- tion that the receiver and transmitter equally divides the maximum total error. there are two possible sources fo r the receivers baud rate erro r. the receiver?s system clock (xtal) will always have some minor instabilit y over the supply voltage range and the tempera- ture range. when using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. the second source for the error is more controllable. the baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. in th is case an ubrrn value that gives an acceptable low error can be used if possible. 17.10 multi-processor communication mode setting the multi-processor communication m ode (mpcmn) bit in ucsr na enables a filtering function of incoming frames received by the usartn receiver. frames that do not contain address information will be ignored and not put into the receive buffer. this effectively reduces the number of incoming frames that has to be handled by the cpu, in a system with multiple mcus that communicate via the same serial bu s. the transmitter is unaffected by the mpcmn setting, but has to be used differently when it is a part of a system utilizing the multi-processor communication mode. table 17-2. recommended maximum receiver baud rate error for normal speed mode (u2xn = 0) d # (data + parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 table 17-3. recommended maximum receiver baud rate error for double speed mode (u2xn = 1) d # (data + parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 194 7679h?can?08/08 at90can32/64/128 17.10.1 mpcm protocol if the receiver is set up to receive frames that c ontain 5 to 8 data bits, then the first stop bit indi- cates if the frame contains data or address information. if the receiver is set up for frames with nine data bits, then the ninth bit (rxb8n) is used for identifying address and data frames. when the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. when the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables several slave mcus to receive data from a master mcu. this is done by first decoding an address frame to find out which mcu has been addressed. if a particular slave mcu has been addressed, it will receive the following data frames as normal, while the other slave mcus will ignore the received frames until another address frame is received. 17.10.2 using mpcm for an mcu to act as a master mcu, it can us e a 9-bit character frame format (ucszn = 7). the ninth bit (txb8n) must be set when an address frame (txb8n = 1) or cleared when a data frame (txbn = 0) is being transmitted. the slave mcus mu st in this case be se t to use a 9-bit charac- ter frame format. the following procedure should be used to exchange data in multi-processor communication mode: 1. all slave mcus are in multi-proc essor communication mode (mpcmn in ucsrna is set). 2. the master mcu sends an address frame, and all slaves receive and read this frame. in the slave mcus, the rxcn flag in ucsrna will be set as normal. 3. each slave mcu reads the udrn register and determines if it has been selected. if so, it clears the mpcmn bit in ucsrna, otherwise it waits for the next address byte and keeps the mpcmn setting. 4. the addressed mcu will receive all data fram es until a new address frame is received. the other slave mcus, which still have the mp cmn bit set, will ignore the data frames. 5. when the last data frame is received by the addressed mcu, the addressed mcu sets the mpcmn bit and waits for a new address frame from master. the process then repeats from 2. using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change between using n and n+1 character frame formats. this makes full- duplex operation difficult since th e transmitter and receiver use the same character size set- ting. if 5- to 8-bit character frames are used, the transmitter must be set to use two stop bit (usbsn = 1) since the first stop bit is used for indicating the frame type. 195 7679h?can?08/08 at90can32/64/128 17.11 usart regist er description 17.11.1 usart0 i/o da ta register ? udr0 17.11.2 usart1 i/o da ta register ? udr1 ? bit 7:0 ? rxbn7:0: receive data buffer (read access) ? bit 7:0 ? txbn7:0: transmit data buffer (write access) the usartn transmit data buffe r register and usartn receive data buffer registers share the same i/o address referred to as usartn data register or udrn. the transmit data buffer register (txbn) will be the destination for data written to the udrn register location. reading the udrn register location will re turn the contents of the receiv e data buffer register (rxbn). for 5-, 6-, or 7-bi t characters the upper unus ed bits will be ignored by the transmitter and set to zero by the receiver. the transmit buffer can only be written when the udren flag in the ucsrna register is set. data written to udrn when the udren flag is not set, will be ignored by the usartn transmit- ter. when data is written to the transmit buffer, and the transmitter is enabled, the transmitter will load the data into the transmit shift regist er when the shift regist er is empty. then the data will be serially transmitted on the txdn pin. the receive buffer consists of a two level fifo . the fifo will change its state whenever the receive buffer is accessed. 17.11.3 usart0 control and status register a ? ucsr0a 17.11.4 usart1 control and status register a ? ucsr1a ? bit 7 ? rxcn: usartn receive complete this flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread dat a). if the receiver is disabled, the receive buffer will be flushed and consequently the rxcn bit will become zero. the rxcn flag can be used to generate a receive complete interr upt (see description of the rxcien bit). bit 76543210 rxb0[7:0] udr0 (read) txb0[7:0] udr0 (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 rxb1[7:0] udr1 (read) txb1[7:0] udr1 (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 ucsr0a read/write r r/w r r r r r/w r/w initial value00100000 bit 76543210 rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 ucsr1a read/write r r/w r r r r r/w r/w initial value00100000 196 7679h?can?08/08 at90can32/64/128 ? bit 6 ? txcn: usartn transmit complete this flag bit is set when the en tire frame in the transmit shift register has been shifted out and there are no new data currently present in the tran smit buffer (udrn). the txcn flag bit is auto- matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. the txcn flag can generate a transmit complete interrupt (see descrip- tion of the txcien bit). ? bit 5 ? udren: usartn data register empty the udren flag indicates if the transmit buffer (udr n) is ready to receiv e new data. if udren is one, the buffer is empty, and therefore ready to be written. the udren flag can generate a data register empty interrupt (see de scription of the udrien bit). udren is set after a reset to indica te that the transmitter is ready. ? bit 4 ? fen: frame error this bit is set if the next character in the receive buffer had a frame error when received. i.e., when the first stop bit of the next character in th e receive buffer is zero. this bit is valid until the receive buffer (udrn) is read. the fen bit is zero when the stop bit of received data is one. always set this bit to ze ro when writing to ucsrna. ? bit 3 ? dorn: data overrun this bit is set if a data overrun condition is detected. a data overrun occurs when the receive buffer is full (two characters), it is a new char acter waiting in the receive shift register, and a new start bit is detected. this bi t is valid until the receive buffer (udrn) is read . always set this bit to zero when writing to ucsrna. ? bit 2 ? upen: usartn parity error this bit is set if the next character in the receive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. always set this bit to zero when writing to ucsrna. ? bit 1 ? u2xn: double the usartn transmission speed this bit only has effect for the asynchronous operation. write this bit to zero when using syn- chronous operation. writing this bit to one will reduce the divisor of th e baud rate divider from 16 to 8 effectively dou- bling the transfer rate for asynchronous communication. ? bit 0 ? mpcmn: multi-processor communication mode this bit enables the multi-processor communica tion mode. when the mpcmn bit is written to one, all the incoming frames received by t he usarnt receiver that do not contain address information will be ignored. th e transmitter is unaffected by the mpcmn setting. for more detailed information see ?multi-processor communication mode? on page 193 . 17.11.5 usart0 control and status register b ? ucsr0b bit 76543210 rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 ucsr0b read/write r/w r/w r/w r/w r/w r/w r r/w initial value00000000 197 7679h?can?08/08 at90can32/64/128 17.11.6 usart1 control and status register b ? ucsr1b ? bit 7 ? rxcien: rx co mplete interrupt enable writing this bit to one enables interrupt on th e rxcn flag. a usartn receive complete inter- rupt will be generate d only if the rxcien bit is written to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set. ? bit 6 ? txcien: tx complete interrupt enable writing this bit to one enables interrupt on the txcn flag. a usartn transmit complete inter- rupt will be generate d only if the txcien bit is written to one, the global interrupt flag in sreg is written to one and the tx cn bit in ucsrna is set. ? bit 5 ? udrien: usartn data register empty interrupt enable writing this bit to one enables interrupt on the udren flag. a da ta register empty interrupt will be generated only if the udrien bit is written to o ne, the global interrupt flag in sreg is written to one and the udren bit in ucsrna is set. ? bit 4 ? rxenn: receiver enable writing this bit to one enables the usartn rece iver. the receiver will override normal port operation for the rxdn pin when enabled. disabl ing the receiver will fl ush the receive buffer invalidating the fen, dorn, and upen flags. ? bit 3 ? txenn: transmitter enable writing this bit to one enables the usartn transmitter. the transmi tter will override normal port operation for the txdn pin when enabled. the disabling of the transmitter (writing txenn to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit shift register and transmit buffe r register do not contain data to be trans- mitted. when disabled, the transmitter will no longer override the txdn port. ? bit 2 ? ucszn2: character size the ucszn2 bits combined with the ucszn1:0 bi t in ucsrnc sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 1 ? rxb8n: receive data bit 8 rxb8n is the ninth data bit of the received char acter when operating with serial frames with nine data bits. must be read before reading the low bits from udrn. ? bit 0 ? txb8n: transmit data bit 8 txb8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. must be written before writing the low bits to udrn. 17.11.7 usart0 control and status register c ? ucsr0c bit 76543210 rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 ucsr1b read/write r/w r/w r/w r/w r/w r/w r r/w initial value00000000 bit 76543210 ? umsel0 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 ucsr0c read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000110 198 7679h?can?08/08 at90can32/64/128 17.11.8 usart1 control and status register c ? ucsr1c ? bit 7 ? reserved bit this bit is reserved for future use. for compatib ility with future devices, these bit must be written to zero when ucsrnc is written. ? bit 6 ? umseln: usartn mode select this bit selects between asynchronous and synchronous mode of operation. ? bit 5:4 ? upmn1:0: parity mode these bits enable and set type of parity generati on and check. if enabled, the transmitter will automatically generate and send t he parity of the transmitted data bits within each frame. the receiver will generate a pari ty value for the incoming data an d compare it to the upmn0 setting. if a mismatch is detected, the upen flag in ucsrna will be set. ? bit 3 ? usbsn: stop bit select this bit selects the number of stop bits to be in serted by the transmitter. the receiver ignores this setting. bit 76543210 ? umsel1 upm11 upm10 usbs1 ucsz11 ucsz10 ucpo1l ucsr1c read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000110 table 17-4. umseln bit settings umseln mode 0 asynchronous operation 1 synchronous operation table 17-5. upmn bits settings upmn1 upmn0 parity mode 0 0 disabled 01reserved 1 0 enabled, even parity 1 1 enabled, odd parity table 17-6. usbsn bit settings usbsn stop bit(s) 01-bit 12-bit 199 7679h?can?08/08 at90can32/64/128 ? bit 2:1 ? ucszn1:0: character size the ucszn1:0 bits combined with the ucszn2 bit in ucsrnb sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 0 ? ucpoln: clock polarity this bit is used for synchronous mode only. write this bit to zero when asynchronous mode is used. the ucpoln bit sets the relationship betwee n data output change and data input sample, and the synchronous clock (xckn). 17.11.9 usart0 baud rate registers ? ubrr0l and ubrr0h 17.11.10 usart1 baud rate registers ? ubrr1l and ubrr1h table 17-7. ucszn bits settings ucszn2 ucszn1 ucszn0 character size 0005-bit 0016-bit 0107-bit 0118-bit 100reserved 101reserved 110reserved 1119-bit table 17-8. ucpoln bit settings ucpoln transmitted data changed (output of txdn pin) received data sampled (input on rxdn pin) 0 rising xck edge falling xck edge 1 falling xck edge rising xck edge bit 151413121110 9 8 ? ? ? ? ubrr0[11:8] ubrr0h ubrr0[7:0] ubrr0l 76543210 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 bit 151413121110 9 8 ? ? ? ? ubrr1[11:8] ubrr1h ubrr1[7:0] ubrr1l 76543210 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 200 7679h?can?08/08 at90can32/64/128 ? bit 15:12 ? reserved bits these bits are reserved for future use. for com patibility with future devi ces, these bit must be written to zero when ubrrnh is written. ? bit 11:0 ? ubrrn11:0: usartn baud rate register this is a 12-bit register which contains t he usartn baud rate. the ubrrnh contains the four most significant bits, and the ubrrnl contains the eight least significant bits of the usartn baud rate. ongoing transmissions by the tran smitter and receiver will be corrupted if the baud rate is changed. writing ubrr nl will trigger an immediate update of the baud ra te prescaler. 17.12 examples of ba ud rate setting for standard crystal, resonator and external os cillator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the ubrrn settings in table 17-9 up to table 17-12 . ubrrn values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. higher error ratings are acceptable, but the receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see ?asynchronous operational range? on page 192 ). the error values are calcu- lated using the following equation: note: 1. ubrrn = 0, error = 0.0% error[%] 1 baudrate closest match baudrate -------------------------------------------------------- ? ?? ?? 100% ? = table 17-9. examples of ubrrn settings for commonly frequencies baud rate (bps) f clk io = 1.0000 mhz f clk io = 1.8432 mhz f clk io = 2.0000 mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k ? ? 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k ? ? 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k??????00.0%???? 250k ???????????? 500k ???????????? 1m ???????????? max. (1) 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kbps 250 kbps 201 7679h?can?08/08 at90can32/64/128 note: 1. ubrrn = 0, error = 0.0% table 17-10. examples of ubrrn settings for commonly frequencies (continued) baud rate (bps) f clk io = 3.6864 mhz f clk io = 4.0000 mhz f clk io = 7.3728 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 500k ? ? 0 -7.8% ? ? 0 0.0% 0 -7.8% 1 -7.8% 1m ??????????0-7.8% max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 mbps 460.8 kbps 921.6 kbps 202 7679h?can?08/08 at90can32/64/128 note: 1. ubrrn = 0, error = 0.0% table 17-11. examples of ubrrn settings for commonly frequencies (continued) baud rate (bps) f clk io = 8.0000 mhz f clk io = 10.000 mhz f clk io = 11.0592 mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 207 0.2% 416 -0.1% 259 0.2% 520 0.0% 287 0.0% 575 0.0% 4800 103 0.2% 207 0.2% 129 0.2% 259 0.2% 143 0.0% 287 0.0% 9600 51 0.2% 103 0.2% 64 0.2% 129 0.2% 71 0.0% 143 0.0% 14.4k 34 -0.8% 68 0.6% 42 0.9% 86 0.2% 47 0.0% 95 0.0% 19.2k 25 0.2% 51 0.2% 32 -1.4% 64 0.2% 35 0.0% 71 0.0% 28.8k 16 2.1% 34 -0.8% 21 -1.4% 42 0.9% 23 0.0% 47 0.0% 38.4k 12 0.2% 25 0.2% 15 1.8% 32 -1.4% 17 0.0% 35 0.0% 57.6k 8 -3.5% 16 2.1% 10 -1.5% 21 -1.4% 11 0.0% 23 0.0% 76.8k 6 -7.0% 12 0.2% 7 1.9% 15 1.8% 8 0.0% 17 0.0% 115.2k 3 8.5% 8 -3.5% 4 9.6% 10 -1.5% 5 0.0% 11 0.0% 230.4k 1 8.5% 3 8.5% 2 -16.8% 4 9.6% 2 0.0% 5 0.0% 250k 1 0.0% 3 0.0% 2 -33.3% 4 0.0% 2 -7.8% 5 -7.8% 500k 0 0.0% 1 0.0% ? ? 2 -33.3% ? ? 2 -7.8% 1m ??00.0%???????? max. (1) 0.5 mbps 1 mbps 625 kbps 1.25 mbps 691.2 kbps 1.3824 mbps 203 7679h?can?08/08 at90can32/64/128 note: 1. ubrrn = 0, error = 0.0% table 17-12. examples of ubrrn settings for commonly frequencies (continued) baud rate (bps) f clk io = 12.0000 mhz f clk io = 14.7456 mhz f clk io = 16.0000 mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 312 -0.2% 624 0.0% 383 0.0% 767 0.0% 416 -0.1% 832 0.0% 4800 155 0.2% 312 -0.2% 191 0.0% 383 0.0% 207 0.2% 416 -0.1% 9600 77 0.2% 155 0.2% 95 0.0% 191 0.0% 103 0.2% 207 0.2% 14.4k 51 0.2% 103 0.2% 63 0.0% 127 0.0% 68 0.6% 138 -0.1% 19.2k 38 0.2% 77 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 28.8k 25 0.2% 51 0.2% 31 0.0% 63 0.0% 34 -0.8% 68 0.6% 38.4k 19 -2.5% 38 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 57.6k 12 0.2% 25 0.2% 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 76.8k 9 -2.7% 19 -2.5% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 115.2k 6 -8.9% 12 0.2% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 230.4k 2 11.3% 6 -8.9% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 250k 2 0.0% 5 0.0% 3 -7.8% 6 5.3% 3 0.0% 7 0.0% 500k ? ? 2 0.0% 1 -7.8% 3 -7.8% 1 0.0% 3 0.0% 1m ????0-7.8%1-7.8%00.0%10.0% max. (1) 750 kbps 1.5 mbps 921.6 kbps 1.8432 mbps 1 mbps 2 mbps 204 7679h?can?08/08 at90can32/64/128 18. two-wire serial interface 18.1 features ? simple yet powerful and flexible communication interface, only two bus lines needed ? both master and slave operation supported ? device can operate as transmitter or receiver ? 7-bit address space allows up to 128 different slave addresses ? multi-master arbitration support ? up to 400 khz data transfer speed ? slew-rate limited output drivers ? noise suppression circuitry rejects spikes on bus lines ? fully programmable slave address with general call support ? address recognition causes wake-up when avr is in sleep mode 18.2 two-wire serial in terface bus definition the two-wire serial interface (twi) is ideally suited for typical microc ontroller applications. the twi protocol allows the systems designer to in terconnect up to 128 different devices using only two bi-directional bus lines, one for clock (scl) and one for data (sda). the only external hard- ware needed to implement the bus is a single pull- up resistor for each of the twi bus lines. all devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the twi protocol. figure 18-1. twi bus interconnection 18.2.1 twi terminology the following definitions are frequently encountered in this section. device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc table 18-1. twi terminology term description master the device that initiates and terminates a transmission. the master also generates the scl clock slave the device addressed by a master transmitter the device placing data on the bus receiver the device reading data from the bus 205 7679h?can?08/08 at90can32/64/128 18.2.2 electrical interconnection as depicted in figure 18-1 , both bus lines are connected to the positive supply voltage through pull-up resistors. the bus driver s of all twi-compliant devices are open-drain or open-collector. this implements a wired-and functi on which is essential to the o peration of the interface. a low level on a twi bus line is generated when one or more twi devices output a zero. a high level is output when all twi devices tri-state their outputs, allowing the pull-up resistors to pull the line high. note that all avr devices connected to the twi bus must be powered in order to allow any bus operation. the number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pf and the 7-bit slave address space. a detailed specification of the electrical char- acteristics of the twi is given in ?two-wire serial interface characteristics? on page 369 . two different sets of specif ications are presented t here, one relevant for bus speeds below 100 khz, and one valid for bus speeds up to 400 khz. 18.3 data transfer and frame format 18.3.1 transferring bits each data bit transferred on the twi bus is accompanied by a pulse on the clock line. the level of the data line must be stable when the clock line is high. the only exception to this rule is for generating start and stop conditions. figure 18-2. data validity 18.3.2 start and stop conditions the master initiates and terminates a data transmission. the trans mission is initiated when the master issues a start condition on the bus, and it is terminated when the master issues a stop condition. between a start and a stop condition, the bus is considered busy, and no other master should try to seize control of t he bus. a special case occurs when a new start condition is issued between a start and stop condition. this is referred to as a repeated start condition, and is used when the master wis hes to initiate a new transfer without relin- quishing control of the bus. after a repeated start, the bus is cons idered busy until the next stop. this is identical to the start behaviour , and therefore start is used to describe both start and repeated start for the remainder of this datasheet, unless otherwise noted. as depicted below, start and stop conditions are signalled by changing the level of the sda line when the scl line is high. sda scl data stable data stable data change 206 7679h?can?08/08 at90can32/64/128 figure 18-3. start, repeated start and stop conditions 18.3.3 address packet format all address packets transmitted on the twi bus ar e 9 bits long, consisting of 7 address bits, one read/write control bit and an acknowledge bit. if the read/write bit is set, a read opera- tion is to be performed, otherwise a write operation should be performed. when a slave recognizes that it is being a ddressed, it should acknowledge by pulling sda low in the ninth scl (ack) cycle. if the addressed sl ave is busy, or for some other reason can not service the mas- ter?s request, the sda line should be left high in the ack clock cycle. the master can then transmit a stop condition, or a repeated start condition to in itiate a new tr ansmission. an address packet consisting of a slave address and a read or a write bit is called sla+r or sla+w, respectively. the msb of the address byte is transmitted first. slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. when a general call is issued, all slaves should respond by pulling the sda line low in the ack cycle. a general call is used when a master wi shes to transmit the same message to several slaves in the system. when the general call addr ess followed by a write bit is transmitted on the bus, all slaves set up to ackn owledge the general call will pull th e sda line low in the ack cycle. the following data packets will then be received by all the slaves that acknowle dged the general call. note that transmitting the general call add ress followed by a read bit is meaningless, as this would cause contention if several slaves started transmitting different data. all addresses of the format 1111 xxx should be reserved for future purposes. figure 18-4. address packet format 18.3.4 data packet format all data packets transmitted on the twi bus are 9 bits long, consisting of one data byte and an acknowledge bit. during a data transfer, the master generates the clock and the start and stop conditions, while the re ceiver is responsible for acknowledging the reception. an sda scl start stop repeated start stop start sda scl start 12 789 addr msb addr lsb r/w ack 207 7679h?can?08/08 at90can32/64/128 acknowledge (ack) is signalled by the receiver pulling the sda line low during the ninth scl cycle. if the receiver leaves the sda line high, a nack is signalled. when the receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the transmitter by sending a nack afte r the final byte. the msb of the data byte is transmitted first. figure 18-5. data packet format 18.3.5 combining address and data packets into a transmission a transmission basically consists of a start co ndition, a sla+r/w, one or more data packets and a stop condition. an empty message, consisting of a start followed by a stop condi- tion, is illegal. note that the wired-anding of the sc l line can be used to implement handshaking between the master and the slave. the slave can extend the scl low period by pulling the scl line low. this is useful if the cloc k speed set up by the master is too fast for the slave, or the slave needs extra time for processing between the data transmissions. the slave extending the scl low period will not affect t he scl high period, which is determined by the master. as a consequence, the slave can reduce the twi data tr ansfer speed by prolonging the scl duty cycle. figure 18-6 shows a typical data transmission. note that several data bytes can be transmitted between the sla+r/w and the stop condition, depending on the software protocol imple- mented by the application software. figure 18-6. typical data transmission 18.4 multi-master bus systems, ar bitration and synchronization the twi protocol allows bus s ystems with several masters. s pecial concerns have been taken in order to ensure that transmis sions will proceed as normal, even if two or more masters initiate a transmission at the same time. two pr oblems arise in mu lti-master systems: 12 789 data msb data lsb ack aggregate sda sda from transmitter sda from receiver scl from master sla+r/w data byte stop, repeated start or next data byte 12 789 data byte data msb data lsb ack sda scl start 12 789 addr msb addr lsb r/w ack sla+r/w stop 208 7679h?can?08/08 at90can32/64/128 ? an algorithm must be implemented allowing only one of the masters to complete the transmission. all other masters should cease tran smission when they discover that they have lost the selection process. this selection pr ocess is called arbitration. when a contending master discovers that it has lost the arbitratio n process, it should imm ediately switch to slave mode to check whether it is being addressed by the winning master. th e fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e., the data being transferred on the bus must not be corrupted. ? different masters may use different scl frequencies. a scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. this will fac ilitate the arbitration process. the wired-anding of the bus lines is used to solv e both these problems. the serial clocks from all masters will be wired-anded, yielding a co mbined clock with a high period equal to the one from the master with the shorte st high period. the low period of the combined clock is equal to the low period of the master with the longest low per iod. note that all ma sters listen to the scl line, effectively starting to count their scl high and low time-out periods when the combined scl line goes high or low, respectively. figure 18-7. scl synchronization between multiple masters arbitration is carried out by all masters cont inuously monitoring the sda line after outputting data. if the value read from the sda line does not match the value the master had output, it has lost the arbitration. note that a master can only lose arbitration when it outputs a high sda value while another master outputs a low value. the lo sing master should immediately go to slave mode, checking if it is being addressed by the winning master. the sda line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. arbitration will cont inue until only one master re mains, and this may take many bits. if several masters are trying to address the same slave, ar bitration will cont inue into the data packet. ta low ta high scl from master a scl from master b scl bus line tb low tb high masters start counting low period masters start counting high period 209 7679h?can?08/08 at90can32/64/128 figure 18-8. arbitration between two masters note that arbitration is not allowed between: ? a repeated start condition and a data bit ? a stop condition and a data bit ? a repeated start and a stop condition it is the user software?s responsibility to ensur e that these illegal arbi tration conditions never occur. this implies that in multi-master system s, all data transfers must use the same composi- tion of sla+r/w and data packets. in other words: all transmissions must contain the same number of data packets, otherwise the re sult of the arbitration is undefined. 18.5 overview of the twi module the twi module is comprised of several submodules, as shown in figure 18-9 . all registers drawn in a thick line are accessible through the avr data bus. sda from master a sda from master b sda line synchronized scl line start master a loses arbitration, sda a sda 210 7679h?can?08/08 at90can32/64/128 figure 18-9. overview of the twi module 18.5.1 scl and sda pins these pins interface the avr twi with the rest of the mcu system. the output drivers contain a slew-rate limiter in order to conform to the twi specification. the input stages contain a spike suppression unit removing spikes shorter than 50 ns. note that the internal pullups in the avr pads can be enabled by setting the port bits corresponding to the scl and sda pins, as explained in the i/o port section. the internal pull-ups can in some systems eliminate the need for external ones. 18.5.2 bit rate generator unit this unit controls the period of scl when oper ating in a master mode. the scl period is con- trolled by settings in the twi bit rate register (twbr) and the prescaler bits in the twi status register (twsr). slave operation does not depend on bit rate or prescaler settings, but the cpu clock frequency in the slave must be at least 16 times higher than the scl frequency. note that slaves may prolong the scl low period, thereby reducing the average twi bus clock period. the scl frequency is generated according to the following equation: ? twbr = value of the twi bit rate register ? twps = value of the prescaler bits in the twi status register note: twbr should be 10 or higher if the twi operates in master mode. if twbr is lower than 10, the master may produce an incorrect output on sda an d scl for the reminder of the byte. the prob- lem occurs when operating the twi in master mode, sending start + sla + r/w to a slave (a slave does not need to be connected to the bus for the condition to happen). twi unit address register (twar) address match unit address comparator control unit control register (twcr) status register (twsr) state machine and status control scl slew-rate control spike filter sda slew-rate control spike filter bit rate generator bit rate register (twbr) prescaler bus interface unit start / stop control arbitration detection ack spike suppression address/data shift register (twdr) scl frequency clkio 16 2(twbr) 4 twps ? + ----------------------------------------------------------- = 211 7679h?can?08/08 at90can32/64/128 18.5.3 bus interface unit this unit contains the data and address shif t register (twdr), a start/stop controller and arbitration detection hardware. the twdr contains the address or data bytes to be transmitted, or the address or data bytes received. in additi on to the 8-bit twdr, the bus interface unit also contains a register containing th e (n)ack bit to be transmitted or received. this (n)ack regis- ter is not directly accessible by the application software. however, when re ceiving, it can be set or cleared by manipulating the twi control r egister (twcr). when in transmitter mode, the value of the received (n)ack bit can be determined by the value in the twsr. the start/stop controller is responsible for gene ration and dete ction of start, repeated start, and stop conditions. th e start/stop controller is able to detect start and stop conditions even when the avr mcu is in one of the sleep modes, enabling the mcu to wake up if addressed by a master. if the twi has initiated a transmission as mast er, the arbitration detection hardware continu- ously monitors the transmission trying to determi ne if arbitration is in process. if the twi has lost an arbitration, the control unit is informed. correct action can then be taken and appropriate status codes generated. 18.5.4 address match unit the address match unit checks if received ad dress bytes match the 7-bit address in the twi address register (twar). if the twi general call recognition enable (twgce) bit in the twar is written to one, all incoming address bits will also be compared against the general call address. upon an address match, the control unit is informed, allowing correct action to be taken. the twi may or may not acknowledge it s address, depending on settings in the twcr. the address match unit is able to compare addresses even when the avr mcu is in sleep mode, enabling the mcu to wake up if addresse d by a master. if another interrupt (e.g., int0) occurs during twi power-down address match and wakes up the cpu, the twi aborts opera- tion and return to it?s idle state. if this cause any problems, ensure that twi address match is the only enabled interrupt when entering power-down. 18.5.5 control unit the control unit monitors the twi bus and generates responses corresponding to settings in the twi control register (twcr). when an event requiring the attention of the application occurs on the twi bus, the twi interrupt flag (twint) is asserted. in the next clock cycle, the twi sta- tus register (twsr) is updated with a stat us code identifying the event. the twsr only contains relevant status information when the tw i interrupt flag is assert ed. at all other times, the twsr contains a special stat us code indicating that no relevant status information is avail- able. as long as the twint flag is set, the scl line is held low. this allows the application software to complete its tasks before a llowing the twi transmission to continue. the twint flag is set in the following situations: ? after the twi has transmitted a start/repeated start condition ? after the twi has transmitted sla+r/w ? after the twi has transmitted an address byte ? after the twi has lost arbitration ? after the twi has been addressed by own slave address or general call ? after the twi has received a data byte ? after a stop or repeated start has been received while still addressed as a slave 212 7679h?can?08/08 at90can32/64/128 ? when a bus error has occu rred due to an illegal st art or stop condition 18.6 twi register description 18.6.1 twi bit rate register ? twbr ? bits 7.0 ? twi bit rate register twbr selects the division factor for the bit rate generator. the bit rate generator is a frequency divider which generates the scl clock frequency in the master modes. see ?bit rate generator unit? on page 210 for calculating bit rates. 18.6.2 twi control register ? twcr the twcr is used to control the operation of the twi. it is used to enable the twi, to initiate a master access by applying a start condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control haltin g of the bus while the data to be written to the bus are written to the twdr. it also indicates a write collision if data is attempte d written to twdr while the regist er is inaccessible. ? bit 7 ? twint: twi interrupt flag this bit is set by hardware when the twi has finished its current job and expects application software response. if the i-bit in sreg and tw ie in twcr are set, the mcu will jump to the twi interrupt vector. while the twint flag is se t, the scl low period is stretched. the twint flag must be cleared by software by writing a logic one to it. note that this flag is not automati- cally cleared by hardware when executing the interr upt routine. also note that clearing this flag starts the operation of the twi, so all access es to the twi address register (twar), twi sta- tus register (twsr), and twi data register (twdr) must be complete before clearing this flag. ? bit 6 ? twea: twi enable acknowledge bit the twea bit controls the generation of the ack pulse. if the twea bit is written to one, the ack pulse is generated on the twi bus if the following conditions are met: 1. the device?s own slave add ress has been received. 2. a general call has been received, while the twgce bit in the twar is set. 3. a data byte has been received in master receiver or slave receiver mode. by writing the twea bit to zero, the device can be virtually disconnected from the two-wire serial bus temporarily. address recognition can then be resumed by writing the twea bit to one again. ? bit 5 ? twsta: twi start condition bit bit 76543210 twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 twbr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 twint twea twsta twsto twwc twen ? twie twcr read/write r/w r/w r/w r/w r r/w r r/w initial value00000000 213 7679h?can?08/08 at90can32/64/128 the application writes the twsta bit to one w hen it desires to become a master on the two- wire serial bus. the twi hardware checks if th e bus is available, and generates a start con- dition on the bus if it is free. however, if the bus is not free, t he twi waits until a stop condition is detected, and then generates a new start condition to claim the bus master status. twsta must be cleared by software when the start condition has been transmitted. ? bit 4 ? twsto: twi stop condition bit writing the twsto bit to one in master mode will generate a stop condition on the two-wire serial bus. when the stop c ondition is executed on the bus, the twsto bit is cleared auto- matically. in slave mode, setting the twsto bit can be used to recover from an error condition. this will not generate a stop co ndition, but the twi returns to a well-defined unaddressed slave mode and releases the scl and sda lines to a high impedance state. ? bit 3 ? twwc: twi write collision flag the twwc bit is set when attempting to write to the twi data register ? twdr when twint is low. this flag is cleare d by writing the twdr register when twint is high. ? bit 2 ? twen: twi enable bit the twen bit enables twi operation and activate s the twi interface. wh en twen is written to one, the twi takes control over the i/o pins connected to the scl and sda pins, enabling the slew-rate limiters and spike filters. if this bit is written to zero, the twi is switched off and all twi transmissions are terminated, regardless of any ongoing operation. ? bit 1 ? reserved bit this bit is reserved for future use. for compatibility with future de vices, this must be written to zero when twcr is written. ? bit 0 ? twie: twi interrupt enable when this bit is written to one, and the i-bit in sreg is set, th e twi interrupt request will be acti- vated for as long as the twint flag is high. 18.6.3 twi status register ? twsr ? bits 7.3 ? tws: twi status these 5 bits reflect the status of the twi logic and the two-wire serial bus. the different status codes are described later in this section. note that the value read from twsr contains both the 5-bit status value and the 2-bit prescaler value. the application designer should mask the pres- caler bits to zero when checking the status bits. this makes status checking independent of prescaler setting. this approach is used in this datasheet, unless otherwise noted. ? bit 2 ? res: reserved bit this bit is reserved and will always read as zero. bit 76543210 tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 twsr read/write r r r r r r r/w r/w initial value11111000 214 7679h?can?08/08 at90can32/64/128 ? bits 1.0 ? twps: twi prescaler bits these bits can be read and written, and control the bit rate prescaler. to calculate bit rates, see ?bit rate generator unit? on page 210 . the value of twps1.0 is used in the equation. 18.6.4 twi data register ? twdr in transmit mode, twdr contains the next byte to be transmitted. in receive mode, the twdr contains the last byte received. it is writable while the twi is not in the process of shifting a byte. this occurs when the twi interrupt flag (twint) is set by hardware. note that the data register cannot be initialized by the user before the fi rst interrupt occurs. the data in twdr remains sta- ble as long as twint is set. while data is shif ted out, data on the bus is simultaneously shifted in. twdr always contains the last byte present on the bus, except after a wake up from a sleep mode by the twi interrupt. in this case, the conten ts of twdr is undefined. in the case of a lost bus arbitration, no data is lost in the transition from master to slave. handling of the ack bit is controlled automatically by t he twi logic, the cpu cannot access the ack bit directly. ? bits 7.0 ? twd: twi data register these eight bits constitute the next data byte to be transmitted, or the latest data byte received on the twi serial bus. 18.6.5 twi (slave) address register ? twar ? bits 7.1 ? twa: twi (slave) address register these seven bits constitute the slave address of the twi unit. the twar should be loaded with the 7-bit slave address to which the twi will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. in multimaster systems, twar must be set in masters which can be addressed as slaves by other masters. ? bit 0 ? twgce: twi general call recognition enable bit table 18-2. twi bit rate prescaler twps1 twps0 prescaler value 001 014 1016 1164 bit 76543210 twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 twdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 bit 76543210 twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce twar read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111110 215 7679h?can?08/08 at90can32/64/128 twgce is used to enable recognition of the general call address (0x00). there is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. if a match is found, an interrupt request is generated. if set, this bit enables the recognition of a general call given over the twi serial bus. 18.7 using the twi the avr twi is byte-oriented and interrupt based. interrupts are issued after all bus events, like reception of a byte or transmission of a start condition. because the twi is interrupt-based, the application software is free to carry on othe r operations during a twi byte transfer. note that the twi interrupt enable (twie) bit in twcr to gether with the global interrupt enable bit in sreg allow the application to decide whether or not assertion of the twint flag should gener- ate an interrupt request. if the twie bit is cl eared, the application must poll the twint flag in order to detect actions on the twi bus. when the twint flag is asserted, the twi has finished an operation and awaits application response. in this case, the twi status register (twsr) contains a value indicating the current state of the twi bus. the application software can then decide how the twi should behave in the next twi bus cycle by manipulating the twcr and twdr registers. figure 18-10 is a simple example of how the application can interface to the twi hardware. in this example, a master wishes to transmit a single da ta byte to a slave. this description is quite abstract, a more detailed explanat ion follows later in th is section. a simple code example imple- menting the desired behavior is also presented. figure 18-10. interfacing the application to the twi in a typical transmission 1. the first step in a twi transmission is to transmit a start condition. this is done by writing a specific value into twcr, instructing the twi ha rdware to transmit a start condition. which value to write is described la ter on. however, it is important that the twint bit is set in the value written. writ ing a one to twint clears the flag. the twi will not start any operation as long as the tw int bit in twcr is set. immediately after start sla+w a data a stop 1. application writes to twcr to initiate transmission of start. 2. twint set. status code indicates start condition sent 4. twint set. status code indicates sla+w sendt, ack received 6. twint set. status code indicates data sent, ack received 3. check twsr to see if start was sent. application loads sla+w into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one. 5. check twsr to see if sla+w was sent and ack received. application loads data into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one. 7. check twsr to see if data was sent and ack received. application loads appropriate control signals to send stop into twcr, making sure that twint is written to one. twi bus indicates twint set application action twi hardware action 216 7679h?can?08/08 at90can32/64/128 the application has cleared twint, the tw i will initiate transmission of the start condition. 2. when the start condition has been transmitte d, the twint flag in twcr is set, and twsr is updated with a status code indica ting that the start condition has success- fully been sent. 3. the application software should now examine the value of twsr, to make sure that the start condition was successfully trans mitted. if twsr indicates otherwise, the application software might take some s pecial action, like callin g an error routine. assuming that the status code is as expe cted, the application must load sla+w into twdr. remember that twdr is used both for address and data. after twdr has been loaded with the desired sla+w, a specific value must be written to twcr, instructing the twi hardware to transmit the sla+w present in twdr. which value to write is described later on. however, it is im portant that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. im mediately after the application has cleared twint, the twi will initiate transm ission of the address packet. 4. when the address packet has been transmi tted, the twint flag in twcr is set, and twsr is updated with a status code indica ting that the address packet has success- fully been sent. the status code will also reflect whether a sl ave acknowledged the packet or not. 5. the application software should now examine the value of twsr, to make sure that the address packet was successf ully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some special action, like calling an e rror routine. assuming that the status code is as expected, the application must load a data packet into twdr. subsequently, a specific value must be written to tw cr, instructing the twi hardware to transmit the data packet present in twdr. which value to writ e is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cl eared twint, the twi w ill initiate transmission of the data packet. 6. when the data packet has been transmitt ed, the twint flag in twcr is set, and twsr is updated with a status code indicati ng that the data packet has successfully been sent. the status code will also reflec t whether a slave ackn owledged the packet or not. 7. the application software should now examine the value of twsr, to make sure that the data packet was successfully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some spe- cial action, like calling an erro r routine. assuming that the status code is as expected, the application must write a specific value to twcr, inst ructing the twi hardware to transmit a stop condition. which value to wr ite is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cl eared twint, the twi w ill initiate transmission of the stop condition. note that twint is not set after a stop condition has been sent. even though this example is simple, it shows t he principles involved in all twi transmissions. these can be summarized as follows: ? when the twi has finished an operation and ex pects application response, the twint flag is set. the scl line is pulled low until twint is cleared. 217 7679h?can?08/08 at90can32/64/128 ? when the twint flag is set, the user must u pdate all twi registers with the value relevant for the next twi bus cycle. as an example, twdr must be loaded with the value to be transmitted in the next bus cycle. ? after all twi register updates and other pending application software tasks have been completed, twcr is written. when writing twcr, th e twint bit should be set. writing a one to twint clears the flag. the twi will then commence executing whatever operation was specified by the twcr setting. in the following an assembly and c implementation of the example is give n. note that the code below assumes that several definitions have been made for example by using include-files. assembly code example c example comments 1 ldi r16, (1< 219 7679h?can?08/08 at90can32/64/128 figure 18-11. data transfer in mast er transmitter mode a start condition is sent by wr iting the following value to twcr: twen must be set to enable the two-wire seri al interface, twsta must be written to one to transmit a start condition and twint must be written to one to clear the twint flag. the twi will then test the two-wire serial bus and gene rate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hard- ware, and the status code in twsr will be 0x08 (see table 18-3 ). in order to enter mt mode, sla+w must be transmitted. this is done by writing sla+w to twdr. thereafter the twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to twcr: when sla+w have been transmitted and an ack nowledgment bit has been received, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x18, 0x20, or 0x38. the appropriate action to be taken for each of these status codes is detailed in table 18-3 . when sla+w has been successfully transmitted, a data packet should be transmitted. this is done by writing the data byte to twdr. twdr must only be writ ten when twint is high. if not, the access will be discarded, and the write collision bit (twwc) will be set in the twcr regis- ter. after updating twdr, the twint bit should be cleared (by writing it to one) to continue the transfer. this is acco mplished by writing the following value to twcr: this scheme is repeated until the last byte ha s been sent and the transfer is ended by generat- ing a stop condition or a repeated start conditio n. a stop condition is generated by writing the following value to twcr: a repeated start condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master transmitter slave receiver 220 7679h?can?08/08 at90can32/64/128 after a repeated start condition (state 0x10) the two-wire serial interface can access the same slave again, or a new slave without transmitting a stop c ondition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control of the bus. table 18-3. status codes for master transmitter mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+w x 0 1 x sla+w will be transmitted; ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+w or load sla+r x x 0 0 1 1 x x sla+w will be transmitted; ack or not ack will be received sla+r will be transmitted; logic will switch to master receiver mode 0x18 sla+w has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x20 sla+w has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x28 data byte has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x30 data byte has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x38 arbitration lost in sla+w or data bytes no twdr action or no twdr action 0 1 0 0 1 1 x x two-wire serial bus will be released and not addressed slave mode entered a start condition will be transmitted when the bus be- comes free 221 7679h?can?08/08 at90can32/64/128 figure 18-12. formats and states in the master transmitter mode s sla w a data a p 0x08 0x18 0x28 r sla w 0x10 ap 0x20 p 0x30 a or a 0x38 a other master continues a or a 0x38 other master continues r a 0x68 other master continues 0x78 0xb0 to corresponding states in slave mode mt mr successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero s 222 7679h?can?08/08 at90can32/64/128 18.8.2 master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmitter (see figure 18-13 ). in order to enter a master mode, a start condition must be transmitted. the for- mat of the following address packet determines whether master transmitter or master receiver mode is to be entered. if sla+w is transmitte d, mt mode is entered, if sla+r is transmitted, mr mode is entered. all the st atus codes mentioned in this se ction assume that the prescaler bits are zero or are masked to zero. figure 18-13. data transfer in ma ster receiver mode a start condition is sent by wr iting the following value to twcr: twen must be written to one to enable the tw o-wire serial interface, twsta must be written to one to transmit a start condit ion and twint must be set to clear the twint flag. the twi will then test the two-wire serial bus and generate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hardware, and the status code in twsr will be 0x08 (see table 18-3 ). in order to enter mr mode, sla+r must be transmitted. this is done by writing sla+r to twdr. thereafter the twint bit should be cleared (by writing it to one) to continue the tr ansfer. this is accomplis hed by writing the follow- ing value to twcr: when sla+r have been transmitted and an acknow ledgment bit has been received, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x38, 0x40, or 0x48. the appropriate action to be taken for each of these status codes is detailed in table 18-12 . received data can be read from the twdr register when the twint flag is set high by hardware. this scheme is repe ated until the last byte has been received. after the last byte has been received, the mr should inform the st by sending a nack after the last received data byte. the transfer is ended by generating a stop condition or a repeated start condition. a stop condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master slave transmitter receiver 223 7679h?can?08/08 at90can32/64/128 a repeated start condition is generated by writing the following value to twcr: after a repeated start condition (state 0x10) the two-wire serial interface can access the same slave again, or a new slave without transmitting a stop c ondition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control over the bus. figure 18-14. formats and states in the master receiver mode twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x s sla r a data a 0x08 0x40 0x50 sla r 0x10 ap 0x48 a or a 0x38 other master continues 0x38 other master continues w a 0x68 other master continues 0x78 0xb0 to corresponding states in slave mode mr mt successfull reception from a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p data a 0x58 a r s 224 7679h?can?08/08 at90can32/64/128 18.8.3 slave receiver mode in the slave receiver mode, a number of data by tes are received from a master transmitter (see figure 18-15 ). all the status codes mentio ned in this section assume that the prescaler bits are zero or are masked to zero. figure 18-15. data transfer in slave receiver mode table 18-4. status codes for ma ster receiver mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+r x 0 1 x sla+r will be transmitted ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+r or load sla+w x x 0 0 1 1 x x sla+r will be transmitted ack or not ack will be received sla+w will be transmitted logic will switch to master transmitter mode 0x38 arbitration lost in sla+r or not ack bit no twdr action or no twdr action 0 1 0 0 1 1 x x two-wire serial bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free 0x40 sla+r has been transmitted; ack has been received no twdr action or no twdr action 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x48 sla+r has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x50 data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x58 data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master slave transmitter receiver 225 7679h?can?08/08 at90can32/64/128 to initiate the slave receiver mode, twar and twcr must be initialized as follows: the upper seven bits are the address to which t he two-wire serial interface will respond when addressed by a master. if the lsb is set, the tw i will respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgment of the devic e?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?0? (write), the twi will operate in sr mode, otherwise st mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr. the status c ode is used to determine the appropriate soft- ware action. the appropriate action to be taken for each status code is detailed in table 18-5 . the slave receiver mode may also be entered if ar bitration is lost while the twi is in the master mode (see states 0x68 and 0x78). if the twea bit is reset during a transfer, the tw i will return a ?not acknowledge? (?1?) to sda after the next received data byte. this can be us ed to indicate that t he slave is not able to receive any more bytes. while twea is zero, the twi does not acknowledge its own slave address. however, the two-wire serial bus is still monitored and address recognition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the two-wire serial bus. in all sleep modes other than idle mode, the clo ck system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its own slave ad dress or the general call address by using the two-wire serial bus clock as a clock so urce. the part will then wake up from sleep and the twi will hold the scl clock low during the wake up and until the twint flag is cleared (by writing it to one). further data reception will be carri ed out as normal, with the avr clocks running as normal. observe that if the avr is se t up with a long start-up time, the scl line may be held low for a long time, bl ocking other data transmissions. note that the two-wire serial interface data register ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 226 7679h?can?08/08 at90can32/64/128 table 18-5. status codes for slave receiver mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x60 own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x68 arbitration lost in sla+r/w as mas- ter; own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x70 general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x78 arbitration lost in sla+r/w as mas- ter; general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x80 previously addressed with own sla+w; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x88 previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0x90 previously addressed with general call; data has been re- ceived; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x98 previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xa0 a stop condition or repeated start condition has been received while still addressed as slave read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 227 7679h?can?08/08 at90can32/64/128 figure 18-16. formats and states in the slave receiver mode s sla w a data a 0x60 0x80 0x88 a 0x68 reception of the own slave address and one or more data bytes. all are acknowledged last data byte received is not acknowledged arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes last data byte received is not acknowledged n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data a 0x80 0xa0 p or s a a data a 0x70 0x90 0x98 a 0x78 p or s data a 0x90 0xa0 p or s a general call arbitration lost as master and addressed as slave by general call data a 228 7679h?can?08/08 at90can32/64/128 18.8.4 slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 18-17 ). all the status codes mentio ned in this section assume that the prescaler bits are zero or are masked to zero. figure 18-17. data transfer in slave transmitter mode to initiate the slave transmitter mode, twar and twcr must be in itialized as follows: the upper seven bits are the address to which t he two-wire serial interface will respond when addressed by a master. if the lsb is set, the tw i will respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgment of the devic e?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?1? (read), the twi will operate in st mode, otherw ise sr mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr. the status c ode is used to determine the appropriate soft- ware action. the appropriate action to be taken for each status code is detailed in table 18-6 . the slave transmitter mode may also be entered if arbitration is lost while the twi is in the master mode (see state 0xb0). if the twea bit is written to zero during a transfer, the twi will transm it the last byte of the trans- fer. state 0xc0 or state 0xc8 will be entered, depending on whethe r the master receiver transmits a nack or ack after the final byte. the twi is switched to the not addressed slave mode, and will ignore the master if it continues the transfer. thus the master receiver receives all ?1? as serial data. state 0xc8 is entered if the master demands additional data bytes (by transmitting ack), even though the slave has tran smitted the last byte (twea zero and expect- ing nack from the master). twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master slave transmitter receiver 229 7679h?can?08/08 at90can32/64/128 while twea is zero, the twi does not respond to its own slave address. however, the two-wire serial bus is still monitored an d address recognition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the two-wire serial bus. in all sleep modes other than idle mode, the clo ck system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its own slave ad dress or the general call address by using the two-wire serial bus clock as a clock so urce. the part will then wake up from sleep and the twi will hold the scl clock will low during the wake up and until the twint flag is cleared (by writing it to one). further data tr ansmission will be carried out as normal, with the avr clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long ti me, blocking other data transmissions. note that the two-wire serial interface data register ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. table 18-6. status codes for slave transmitter mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xa8 own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received 0xb0 arbitration lost in sla+r/w as mas- ter; own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received 0xb8 data byte in twdr has been transmitted; ack has been received load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received 0xc0 data byte in twdr has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xc8 last data byte in twdr has been transmitted (twea = ?0?); ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 230 7679h?can?08/08 at90can32/64/128 figure 18-18. formats and states in the slave transmitter mode 18.8.5 miscellaneous states there are two status codes that do not correspond to a defined twi state, see table 18-7 . status 0xf8 indicates that no relevant information is available because the twint flag is not set. this occurs between other states, and when the twi is not involved in a serial transfer. status 0x00 indicates that a bus error has occu rred during a two-wire serial bus transfer. a bus error occurs when a start or stop condition occu rs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. when a bus error occurs, twint is set. to recover from a bus error, the twsto flag must set and twint must be cleared by writing a logic one to it. this causes the twi to enter the not addressed slave mode and to clear the twsto flag (no other bits in twcr are affected). the sda and scl lines are released, and no stop condition is transmitted. s sla r a data a 0xa8 0xb8 a 0xb0 reception of the own slave address and one or more data bytes last data byte transmitted. switched to not addressed slave (twea = ?0?) arbitration lost as master and addressed as slave n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data 0xc0 data a a 0xc8 p or s all 1?s a table 18-7. miscellaneous states status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xf8 no relevant state information available; twint = ?0? no twdr action no twcr action wait or proceed current transfer 0x00 bus error due to an illegal start or stop condition no twdr action 0 1 1 x only the internal har dware is affected, no stop condition is sent on the bus. in all cases, the bus is released and twsto is cleared. 231 7679h?can?08/08 at90can32/64/128 18.8.6 combining several twi modes in some cases, several twi modes must be combined in order to complete the desired action. consider for example reading data from a serial eeprom. typically, such a transfer involves the following steps: 1. the transfer must be initiated 2. the eeprom must be instructed what location should be read 3. the reading must be performed 4. the transfer must be finished note that data is transmitted bo th from master to slave and vice versa. the master must instruct the slave what location it wants to read, requi ring the use of the mt mode. subsequently, data must be read from the slave, implying the use of the mr mode. thus, the transfer direction must be changed. the master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. if this principle is violated in a multimaster sys- tem, another master can alter the data pointer in the eeprom between steps 2 and 3, and the master will read the wrong data lo cation. such a change in transfe r direction is accomplished by transmitting a repeated start between the trans mission of the addres s byte and reception of the data. after a repeated start, the mast er keeps ownership of the bus. the following figure shows the flow in this transfer. figure 18-19. combining several twi modes to access a serial eeprom master transmitter master receiver s = start rs = repeated start p = stop transmitted from master to slave transmitted from slave to master s sla+w a address a rs sla+r a data a p 232 7679h?can?08/08 at90can32/64/128 18.9 multi-master systems and arbitration if multiple masters are connected to the same bus, transmissions may be initiated simulta- neously by one or more of them. the twi standar d ensures that such situations are handled in such a way that one of the mast ers will be allowed to proceed wit h the transfer, and that no data will be lost in the process. an example of an arbitration situat ion is depicted below, where two masters are trying to transmit data to a slave receiver. figure 18-20. an arbitration example several different scenarios may arise du ring arbitration, as described below: ? two or more masters are performing identica l communication with the same slave. in this case, neither the slave nor any of the masters will know about the bus contention. ? two or more masters are accessing the same slave with different data or direction bit. in this case, arbitration will occur, eith er in the read/write bit or in the data bits. the masters trying to output a one on sda while another master outputs a zero will lose the arbitration. losing masters will switch to not addressed slave mode or wait until the bu s is free and transmit a new start condition, depending on application software action. ? two or more masters ar e accessing different slaves. in this case, arbitratio n will occur in the sla bits. masters trying to outp ut a one on sda while another mast er outputs a zero will lose the arbitration. masters losing arbitration in sla will switch to slave mode to check if they are being addressed by the winning master. if addressed, they will switch to sr or st mode, depending on the value of the read/write bit. if they are not being addr essed, they will switch to not addressed slave mode or wait un til the bus is free and transmit a new start condition, depending on ap plication software action. device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master transmitter slave receiver slave receiver 233 7679h?can?08/08 at90can32/64/128 this is summarized in figure 18-21 . possible status values are given in circles. figure 18-21. possible status codes caused by arbitration own address / general call received arbitration lost in sla twi bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free no arbitration lost in data direction yes write data byte will be received and not ack will be returned data byte will be received and ack will be returned last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received read 0xb0 0x68 / 0x78 0x38 sla start data stop 234 7679h?can?08/08 at90can32/64/128 19. controller area network - can the controller area network (can) protocol is a real-time, serial, broadcast protocol with a very high level of security. the at90can32/64/128 ca n controller is fully compatible with the can specification 2.0 part a and part b. it delivers the features required to implement the kernel of the can bus protocol according to the iso/osi reference model: ? the data link layer - the logical link control (llc) sublayer - the medium access control (mac) sublayer ? the physical layer - the physical signalling (pls) sublayer - not supported - the physical medium attach (pma) - not supported - the medium dependent interface (mdi) the can controller is able to handle all types of frames (data, remote, error and overload) and achieves a bitrate of 1 mbit/s. 19.1 features ? full can controller ? fully compliant with can stan dard rev 2.0 a and rev 2.0 b ? 15 mob (message object) with their own: ? 11 bits of identifier tag (rev 2.0 a), 29 bits of identifier tag (rev 2.0 b) ? 11 bits of identifier mask (rev 2.0 a), 29 bits of identifier mask (rev 2.0 b) ? 8 bytes data buffer (static allocation) ? tx, rx, frame buffer or automatic reply configuration ? time stamping ? 1 mbit/s maximum transfer rate at 8 mhz ? ttc timer ? listening mode (for spying or autobaud) 19.2 can protocol the can protocol is an international standard de fined in the iso 11898 for high speed and iso 11519-2 for low speed. 19.2.1 principles can is based on a broadcast communication mechanism. this broad cast communication is achieved by using a message orie nted transmission protocol. these messages are identified by using a message identifier. such a message identifi er has to be unique within the whole network and it defines not only the content but also the priority of the message. the priority at which a message is transmitted compared to another less urgent message is specified by the identifier of each message. the priorities are laid down during system design in the form of corresponding binary values and ca nnot be changed dynamically. the identifier with the lowest binary number has the highest priority. bus access conflicts are resolved by bit-wise arbi tration on the identifiers involved by each node observing the bus level bit for bit. this happens in accordance with the "wired and" mechanism, 235 7679h?can?08/08 at90can32/64/128 by which the dominant state over writes the recessive state. the competition for bus allocation is lost by all nodes with recessive transmission and dominant observation. all the "losers" automat- ically become receivers of the message wit h the highest priority and do not re-attempt transmission until the bus is available again. 19.2.2 message formats the can protocol supports two message frame form ats, the only essential difference being in the length of the identifier. the can standard frame, also known as can 2.0 a, supports a length of 11 bits for the identifier, and the ca n extended frame, also known as can 2.0 b, sup- ports a length of 29 bits for the identifier. 19.2.2.1 can standard frame figure 19-1. can standard frames a message in the can standard frame format begins with the "start of frame (sof)", this is fol- lowed by the "arbitration field" which consist of the identifier and t he "remote transmission request (rtr)" bit used to distinguish between the data frame and the data request frame called remote frame. the following "control field" contains the "identifier extension (ide)" bit and the "data length code (dlc)" used to indicate the number of following data bytes in the "data field". in a remote frame, the dlc contains the number of requested data bytes. the "data field" that follows can hold up to 8 data bytes. the frame integrity is guaranteed by the following "cyclic redundant check (crc)" sum. the "a cknowledge (ack) field" compromises the ack slot and the ack delimiter. the bit in the ack slot is sent as a recessive bit and is overwritten as a dominant bit by the receivers which have at this time received the data correctly. correct mes- sages are acknowledged by the receivers regardles s of the result of the acceptance test. the end of the message is indicated by "end of fr ame (eof)". the "intermission frame space (ifs)" is the minimum number of bits separating cons ecutive messages. if there is no following bus access by any node, the bus remains idle. 11-bit identifier id10..0 interframe space 4-bit dlc dlc4..0 crc del. ack del. 15-bit crc 0 - 8 bytes sof sof rtr ide r0 ack 7 bits intermission 3 bits bus idle bus idle (indefinite) arbitration field data field data frame control field end of frame crc field ack field interframe space 11-bit identifier id10..0 interframe space 4-bit dlc dlc4..0 crc del. ack del. 15-bit crc sof sof rtr ide r0 ack 7 bits intermission 3 bits bus idle bus idle (indefinite) arbitration field remote frame control field end of frame crc field ack field interframe space 236 7679h?can?08/08 at90can32/64/128 19.2.2.2 can extended frame figure 19-2. can extended frames a message in the can extended frame format is likely the same as a message in can standard frame format. the difference is the length of the id entifier used. the identifier is made up of the existing 11-bit identifier (base identifier) and an 18-bit extension (identifier extension). the dis- tinction between can standard frame format an d can extended frame format is made by using the ide bit which is transmitted as dominant in case of a frame in can standard frame format, and transmitted as recessive in the other case. 19.2.2.3 format co-existence as the two formats have to co-exist on one bus, it is laid down which message has higher priority on the bus in the case of bus access collision wi th different formats and the same identifier / base identifier: the message in can standard fr ame format always has priority over the mes- sage in extended format. there are three different types of can modules available: ? 2.0a - considers 29 bit id as an error ? 2.0b passive - ignores 29 bit id messages ? 2.0b active - handles both 11 and 29 bit id messages 19.2.3 can bit timing to ensure correct sampling up to the last bit, a can node needs to re-synchronize throughout the entire frame. this is done at the beginni ng of each message with the falling edge sof and on each recessive to dominant edge. 19.2.3.1 bit construction one can bit time is specified as four non-overlapping time s egments. each segment is con- structed from an integer multiple of the time qu antum. the time quantum or tq is the smallest discrete timing resolution used by a can node. 11-bit base identifier idt28..18 interframe space crc del. ack del. 15-bit crc 0 - 8 bytes sof sof srr ide ack 7 bits intermission 3 bits bus idle bus idle (indefinite) arbitration field arbitration field data field data frame control field control field end of frame crc field ack field interframe space 11-bit base identifier idt28..18 18-bit identifier extension id17..0 18-bit identifier extension id17..0 interframe space 4-bit dlc dlc4..0 crc del. ack del. 15-bit crc sof sof srr ide r0 4-bit dlc dlc4..0 rtr rtr r0 r1 r1 ack 7 bits intermission 3 bits bus idle bus idle (indefinite) remote frame end of frame crc field ack field interframe space 237 7679h?can?08/08 at90can32/64/128 figure 19-3. can bit construction 19.2.3.2 synchronization segment the first segment is used to sy nchronize the various bus nodes. on transmission, at the start of this segment, the current bit level is output. if there is a bit state change between the previous bit and the current bit, then the bus stat e change is expected to occur within this segment by the receiving nodes. 19.2.3.3 propagation time segment this segment is used to compensate for signal de lays across the network. this is necessary to compensate for signal propagation delays on the bus line and through the transceivers of the bus nodes. 19.2.3.4 phase segment 1 phase segment 1 is used to compensate for edge phase errors. this segment may be lengthened during re-synchronization. 19.2.3.5 sample point the sample point is the point of time at which th e bus level is read and interpreted as the value of the respective bit. its lo cation is at the end of phase s egment 1 (between the two phase segments). 19.2.3.6 phase segment 2 this segment is also used to compensate for edge phase errors. this segment may be shortened during re-synchr onization, but the length has to be at least as long as the information processi ng time (ipt) and may not be more than the length of phase segment 1. 19.2.3.7 information processing time it is the time required for the logic to determine the bit level of a sampled bit. time quantum (producer) nominal can bit time segments (producer) sync_seg prop_seg phase_seg_1 phase_seg_2 propagation delay segments (consumer) sync_seg prop_seg phase_seg_1 phase_seg_2 sample point transmission point (producer) can frame (producer) 238 7679h?can?08/08 at90can32/64/128 the ipt begins at the sample point, is measured in tq and is fixed at 2tq for the atmel can. since phase segment 2 also begins at the sample point and is th e last segment in the bit time, ps2 minimum shall not be less than the ipt. 19.2.3.8 bit lengthening as a result of resynchronization, phase s egment 1 may be lengthened or phase segment 2 may be shortened to comp ensate for oscillato r tolerances. if, for example, the transmitter oscilla- tor is slower than the receiver oscillator, the next falling edge used for resynchronization may be delayed. so phase segment 1 is lengthened in order to adjust the sample point and the end of the bit time. 19.2.3.9 bit shortening if, on the other hand, t he transmitter oscillator is faster than the receiver one, the next falling edge used for resynchronization may be too earl y. so phase segment 2 in bit n is shortened in order to adjust the sample point for bit n+1 and the end of the bit time 19.2.3.10 synchroniza tion jump width the limit to the amount of lengthening or shortening of the phase segments is set by the resyn- chronization jump width. this segment may not be longer than phase segment 2. 19.2.3.11 programming the sample point programming of the sample point allows "tuni ng" of the characteristics to suit the bus. early sampling allows more time quanta in the phase segment 2 so the synchronization jump width can be programmed to its maximum. this maximum capacity to shorten or lengthen the bit time decreases the sensitivity to node oscillato r tolerances, so that lo wer cost oscillators such as ceramic resonators may be used. late sampling allows more time quanta in the propagation time segment which allows a poorer bus topology and maximum bus length. 19.2.3.12 synchronization hard synchronization occurs on the recessive-to-do minant transition of the start bit. the bit time is restarted from that edge. re-synchronization occurs when a recessive- to-dominant edge doesn't occur within the syn- chronization segment in a message. 19.2.4 arbitration the can protocol handles bus accesses accordin g to the concept called ?carrier sense multiple access with arbitration on message priority?. during transmission, arbitration on the can bus can be lost to a competing device with a higher priority can identifier. this ar bitration concept avoids collisions of messages whose transmis- sion was started by more than one node simultaneously and makes sure the most important message is sent first without time loss. the bus access conflict is resolved during the arbitration field mostly over the identifier value. if a data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame (c.f. rtr bit). 239 7679h?can?08/08 at90can32/64/128 figure 19-4. bus arbitration 19.2.5 errors the can protocol signals any errors immediatel y as they occur. three error detection mecha- nisms are implemented at the message level and two at the bit level: 19.2.5.1 error at message level ? cyclic redundancy check (crc) the crc safeguards the information in the frame by adding redundant check bits at the transmission end. at the receiver these bits are re-computed and tested against the received bits. if they do not agree there has been a crc error. ?frame check this mechanism verifies the structure of the transmitted frame by ch ecking the bit fields against the fixed format and the frame size. errors detected by frame checks are designated "format errors". ? ack errors as already mentioned frames received are acknowledged by all receivers through positive acknowledgement. if no acknowledgement is rece ived by the transmitte r of the message an ack error is indicated. 19.2.5.2 error at bit level ? monitoring the ability of the transmitter to de tect errors is based on the mo nitoring of bus signals. each node which transmits also observes the bus level and thus detects differences between the bit sent and the bit received. this permits reliable detection of global errors and errors local to the transmitter. ? bit stuffing the coding of the individual bits is tested at bit level. the bit representation used by can is "non return to zero (nrz)" coding, which guar antees maximum efficiency in bit coding. the synchronization edges are generated by means of bit stuffing. 19.2.5.3 error signalling if one or more errors are discovered by at least one node using the above mechanisms, the cur- rent transmission is aborted by sending an "erro r flag". this prevents other nodes accepting the message and thus ensures the consistency of data throughout the network. after transmission of an erroneous message that has been abor ted, the sender automatically re-attempts transmission. node a txcan node b txcan id10 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 sof sof rtr ide can bus - - - - - - - - - arbitration lost node a loses the bus node b wins the bus 240 7679h?can?08/08 at90can32/64/128 19.3 can controller the can controller implemented into at90can32/64/128 offers v2.0b active. this full-can controller provides the whole hardware for convenient acceptance filtering and message management. for each message to be transmitted or received this module contains one so called message object in which all inform ation regarding the message (e.g. identifier, data bytes etc.) are stored. during the initialization of the peripheral, the ap plication defines which messages are to be sent and which are to be received. only if the can controller receives a message whose identifier matches with one of the identifiers of the pr ogrammed (receive-) message objects the message is stored and the application is informed by inte rrupt. another advantage is that incoming remote frames can be answered automatically by the full-can controller with the corresponding data frame. in this way, the cpu load is strong ly reduced compared to a basic-can solution. using full-can controller, high baudrates and high bus loads with many messages can be handled. figure 19-5. can controller structure can channel gen. control gen. status enable mob interrupt bit timing line error can timer lcc mac pls internal txcan internal rxcan mailbox message objets mob0 mob1 mob2 mob i control status idtag+idmask time stamp control status idtag+idmask time stamp control status idtag+idmask time stamp control status idtag+idmask time stamp buffer mob0 buffer mob1 buffer mob2 buffer mob i can data buffers size=120 bytes low priority high priority mob scanning 241 7679h?can?08/08 at90can32/64/128 19.4 can channel 19.4.1 configuration the can channel can be in: ? enabled mode in this mode: ? the can channel (internal txcan & rxcan) is enabled, ? the input clock is enabled. ? standby mode in standby mode: ? the transmitter constantly provides a rece ssive level (on internal txcan) and the receiver is disabled, ? input clock is enabled, ? the registers and pages remain accessible. ? listening mode this mode is transparent for the can channel: ? enables a hardware loop back, internal txcan on internal rxcan ? provides a recessive level on txcan output pin ? does not disable rxcan input pin ? freezes tec and rec error counters figure 19-6. listening mode 19.4.2 bit timing fsm?s (finite state machine) of the can channel need to be synchronous to the time quantum. so, the input clock for bit timing is the clock used into can channel fsm?s. field and segment abbreviations: ? brp: baud rate prescaler. ? tq: time quantum (output of baud rate prescaler). ? syns: synchronization segment is 1 tq long. ? prs: propagation time segment is programmable to be 1, 2, ..., 8 tq long. ? phs1: phase segment 1 is programmable to be 1, 2, ..., 8 tq long. ? phs2: phase segment 2 is programmable to be phs1 and information processing time. ? information processing time is 2 tq. ? sjw: (re) synchronization jump width is programmable between 1 and min(4, phs1). 1 0 pd5 txcan pd6 rxcan internal txcan internal rxcan listen 242 7679h?can?08/08 at90can32/64/128 the total number of tq in a bit time has to be programmed at least from 8 to 25. figure 19-7. sample and transmission point figure 19-8. general structure of a bit period 19.4.3 baud rate with no baud rate prescaler (brp[5..0]=0) t he sampling point comes one time quantum too early. this leads to a fail according the iso1 6845 test plan. it is ne cessary to lengthen the phase segment 1 by one time quantum and to shorten the phase segment 2 by one time quan- tum to compensate. the baud rate selection is made by t bit calculation: tbit (1) = tsyns + tprs + tphs1 + tphs2 1. tsyns = 1 x tscl = (brp[5..0]+ 1)/clk io (= 1tq) 2. tprs = (1 to 8) x tscl = (prs[2..0]+ 1) x tscl 3. tphs1 = (1 to 8) x tscl = (phs1[2..0]+ 1) x tscl 4. tphs2 = (1 to 8) x tscl = (phs2[2..0] (2) + 1) x tscl bit timing sample point transmission point prescaler brp prs (3-bit length) sjw (2-bit length) phs1 (3-bit length) phs2 (3-bit length) clk io fcan (tscl) time quantum bit rate prescaler clk io f can data tscl (tq) 1 / clk io one nominal bit tsyns (5) tphs2+tsjw ( 4 ) tphs1+tsjw ( 3 ) tbit tphs2 ( 2 ) tphs1 ( 1 ) tprs sample point transmission point 5. synchronization segment: syns tsyns=1 x tscl ( fixed ) notes: 1. phase error < 0 2. phase error > 0 3. phase error > 0 4. phase error < 0 or or 243 7679h?can?08/08 at90can32/64/128 5. tsjw = (1 to 4) x tscl = (sjw[1..0]+ 1) x tscl notes: 1. the total number of tscl (time quanta) in a bit time must be from 8 to 25. 2. phs2[2..0] 2 is programmable to be phs1[2..0] and 1. 19.4.4 fault confinement (c.f. section 19.7 ?error management? on page 248 ). 19.4.5 overload frame an overload frame is sent by se tting an overload request (ovrq) . after the next reception, the can channel sends an overload frame in accor dance with the can specif ication. a status or flag is set (ovrg) as long as the overload frame is sent. figure 19-9. overload frame 19.5 message objects the mob is a can frame descriptor. it contains all information to handle a can frame. this means that a mob has been outlined to allow to describe a can message like an object. the set of mobs is the front end part of the ?mailbox? wh ere the messages to send and/or to receive are pre-defined as well as possible to decr ease the work load of the software. the mobs are independent but priority is given to the lower one in case of multi matching. the operating modes are: ? disabled mode ? transmit mode ? receive mode ? automatic reply ? frame buffer receive mode 19.5.1 number of mobs this device has 15 mobs, they are numbered from 0 up to 14 (i=14, no mob 15). ident "a" cmd message data "a" crc interframe a ident "b" overload frame overload frame rxcan setting ovrq bit ovrg bit resetting ovrq bit txcan ovrq bit instructions 244 7679h?can?08/08 at90can32/64/128 19.5.2 operating modes there is no default mode after reset. every mob has its own fields to control t he operating mode. before enabling the can periph- eral, each mob must be configured (e x: disabled mode - conmob=00). 19.5.2.1 disabled in this mode, the mob is ?free?. 19.5.2.2 tx data & remote frame 1. several fields must be initialized before sending: ? identifier tag (idt) ? identifier extension (ide) ? remote transmission request (rtrtag) ? data length code (dlc) ? reserved bit(s) tag (rbntag) ? data bytes of message (msg) 2. the mob is ready to send a data or a remo te frame when the mob configuration is set (conmob). 3. then, the can channel scans all the mobs in tx configur ation, finds the mob having the highest priority and tries to send it. 4. when the transmission is complete d the txok flag is set (interrupt). 5. all the parameters and data are available in the mob until a new initialization. 19.5.2.3 rx data & remote frame 1. several fields must be in itialized before receiving: ? identifier tag (idt) ? identifier mask (idmsk) ? identifier extension (ide) ? identifier extension mask (idemsk) ? remote transmission request (rtrtag) ? remote transmission request mask (rtrmsk) ? data length code (dlc) ? reserved bit(s) tag (rbntag) table 19-1. mob configuration mob configuration reply valid rtr tag operating mode 0 0 x x disabled 01 x 0 tx data frame x 1 tx remote frame 10 x 0 rx data frame 0 1 rx remote frame 1 rx remote frame then, tx data frame (reply) 1 1 x x frame buffer receive mode 245 7679h?can?08/08 at90can32/64/128 2. the mob is ready to receive a data or a remote frame when the mob configuration is set (conmob). 3. when a frame identifier is received on can network, the can channel scans all the mobs in receive mode, tries to find the mo b having the highest priority which is matching. 4. on a hit, the idt, the ide and the dlc of the matched mob are updated from the incoming (frame) values. 5. once the reception is completed, the data bytes of the received message are stored (not for remote frame) in the data buffer of the matched mob and the rxok flag is set (interrupt). 6. all the parameters and data are available in the mob until a new initialization. 19.5.2.4 automatic reply a reply (data frame) to a remote frame can be aut omatically sent after reception of the expected remote frame. 1. several fields must be initialized before receiving the remote frame: ? reply valid (rplv) in a identical flow to the one described in section 19.5.2.3 ?rx data & remote frame? on page 244 . 2. when a remote frame matches, automatically the rtrtag and the reply valid bit (rplv) are reset. no flag (or interrupt) is set at this time . since the can data buffer has not been used by the incoming remote frame, the mob is then ready to be in transmit mode without any more setting. the idt, the ide, the other tags and the dlc of the received remote frame are used for the reply. 3. when the transmission of the reply is co mpleted the txok flag is set (interrupt). 4. all the parameters and data are available in the mob until a new initialization. 19.5.2.5 frame buffer receive mode this mode is useful to receive multi frames. the priority between mobs offers a management for these incoming frames. one set mobs (including non-consecutiv e mobs) is created when the mobs are set in this mode. due to the mode se tting, only one set is possible. a frame buffer completed flag (or interrupt) - bxok - will rise only when all the mobs of the set will have received their dedicated can frame. 1. mobs in frame buffer receive mode need to be initialized as mobs in standard receive mode. 2. the mobs are ready to receive data (or a remote) frames when their respective config- urations are set (conmob). 3. when a frame identifier is received on can network, the can channel scans all the mobs in receive mode, tries to find the mo b having the highest priority which is matching. 4. on a hit, the idt, the ide and the dlc of the matched mob are updated from the incoming (frame) values. 5. once the reception is completed, the data bytes of the received message are stored (not for remote frame) in the data buffer of the matched mob and the rxok flag is set (interrupt). 6. when the reception in the last mob of the set is completed, the frame buffer completed bxok flag is set (interrupt). bxok flag can be cleared only if all conmob fields of the set have been re-written before. 7. all the parameters and data are availabl e in the mobs until a new initialization. 246 7679h?can?08/08 at90can32/64/128 19.5.3 acceptance filter upon a reception hit (i.e., a good comparison between the i d + rtr + rbn + ide received and an idt+ rtrtag + rbntag + ide specified while taking the comparison mask into account) the idt + rtrtag + rb ntag + ide received are updated in the mo b (written over the registers). figure 19-10. acceptance filter block diagram note: examples: full filtering : to accept only id = 0x317 in part a. - id msk = 111 1111 1111 b - id tag = 011 0001 0111 b partial filtering : to accept id from 0x310 up to 0x317 in part a. - id msk = 111 1111 1000 b - id tag = 011 0001 0xxx b no filtering : to accept all id from 0x000 up to 0x7ff in part a. - id msk = 000 0000 0000 b - id tag = xxx xxxx xxxx b 19.5.4 mob page every mob is mapped into a page to save place. the page number is the mob number. this page number is set in canpage register. t he number 15 is reserved for factory tests. canhpmob register gives the mob having the highest priority in cansit regi sters. it is format- ted to provide a direct entry for canpage register. because canhpmob codes cansit registers, it will be only updated if the corresponding enable bits (enrx, entx, enerr) are enabled (c.f. figure 19-14 ). 19.5.5 can data buffers to preserve register allocation, the can dat a buffer is seen such as a fifo (with address pointer accessible) into a mob selection.this al so allows to reduce the risks of un-controlled accesses. there is one fifo per mob. this fifo is accessed into a mob page thanks to the can mes- sage register. canidm registers (mob[i]) idmsk rtrmsk idemsk canidt registers & cancdmob (mob[i]) id & rb rtrtag ide internal rxd can rx shift register (internal) id & rb rtr ide = hit mob[i] 14(33) 13(31) - rb excluded rb excluded 13(31) 14(33) write enable 13(31) 1 247 7679h?can?08/08 at90can32/64/128 the data index (indx) is the address pointer to the required data byte. the data byte can be read or write. the data index is automatically incremented after every access if the ainc* bit is reset. a roll-over is implemented, afte r data index=7 it is data index=0. the first byte of a can frame is stored at the data index=0, the second one at the data index=1, ... 19.6 can timer a programmable 16-bit timer is used for message stamping and time trigger communication (ttc). figure 19-11. can timer block diagram 19.6.1 prescaler an 8-bit prescaler is initialized by cantcon register. it receives the clk io frequency divided by 8. it provides clk cantim frequency to the can timer if the can controller is enabled. t clk cantim = t clk io x 8 x (cantcon [7:0] + 1) 19.6.2 16-bit timer this timer starts counting from 0x0000 when the can controller is enabled (enfg bit). when the timer rolls over from 0xffff to 0x00 00, an interrupt is generated (ovrtim). 19.6.3 time triggering two synchronization modes are implemented for ttc (ttc bit): ? synchronization on start of frame (syncttc=0), ? synchronization on end of frame (syncttc=1). in ttc mode, a frame is sent once, even if an error occurs . 19.6.4 stamping message the capture of the timer value is done in the mo b which receives or sends the frame. all man- aged mob are stamped, the stamping of a received (sent) frame occurs on rxok (txok). clk io clk cantim cantim canttc canstm[i] cantcon ttc syncttc "eof " "sof " ovrtim txok[i] rxok[i] overrun enfg 8 248 7679h?can?08/08 at90can32/64/128 19.7 error management 19.7.1 fault confinement the can channel may be in one of the three following states: ? error active (default): the can channel takes part in bus communication and can send an active error frame when the can macro detects an error. ? error passive: the can channel cannot send an active error frame. it takes part in bus communication, but when an error is detected, a passive error frame is sent. also, after a transmission, an error passive unit will wait before in itiating further transmission. ? bus off: the can channel is not allowed to have any influence on the bus. for fault confinement, a transmit error counte r (tec) and a receive error counter (rec) are implemented. boff and errp bits give the inform ation of the state of the can channel. setting boff to one may generate an interrupt. figure 19-12. line error mode note: more than one rec/tec change may apply during a given message transfer. 19.7.2 error types ? berr : bit error. the bit value which is monitored is different from the bit value sent. note: exceptions: - recessive bit sent monitored as dominant bi t during the arbitration field and the acknowl- edge slot. - detecting a dominant bit during the sending of an error frame. ? serr : stuff error. detection of more than fi ve consecutive bit wit h the same polarity. ? cerr : crc error (rx only). the receiver performs a crc check on every destuffed received message from the start of frame up to the data field. if this checking does not match with the destuffed crc field, an crc error is set. ? ferr : form error. the form error results from one (or more) violations of the fixed form of the following bit fields: ? crc delimiter ? acknowledgement delimiter errp = 1 boff = 0 error active error passive bus off tec > 127 or rec > 127 128 occurrences of 1 1 consecutive recessive bit reset interrupt - boffit tec > 255 tec < 127 and rec < 127 errp = 0 boff = 0 errp = 0 boff = 1 249 7679h?can?08/08 at90can32/64/128 ? end-of-frame ? error delimiter ? overload delimiter ? aerr : acknowledgment error (tx only). no detecti on of the dominant bit in the acknowledge slot. figure 19-13. error detection procedures in a data frame 19.7.3 error setting the can channel can detect some errors on the can network. ? in transmission: the error is set at mob level. ? in reception: - the identified has matched: the error is set at mob level. - the identified has no t or not yet matched: the error is set at general level. after detecting an error, the can channel sends an error frame on network. if the can channel detects an error frame on network, it sends its own error frame. 19.8 interrupts 19.8.1 interrupt organization the different interrupts are: ? interrupt on receive completed ok, ? interrupt on transmit completed ok, ? interrupt on error (bit error, stuff error, crc error, form error, acknowledge error), ? interrupt on frame buffer full, ? interrupt on ?bus off? setting, ? interrupt on overrun of can timer. the general interrupt enable is provided by enit bit and the specific interrupt enable for can timer overrun is provided by enorvt bit. identifier message data rtr ack error form error stuff error bit error crc error form error stuff error bit error ack eof sof crc del. ack del. inter. control crc tx rx arbitration 250 7679h?can?08/08 at90can32/64/128 figure 19-14. can controller interrupt structure 19.8.2 interrupt behavior when an interrupt occurs, an interrupt flag bit is set in the corresponding mob-canstmob reg- ister or in the general cangit register. if in the canie register, enrx / entx / enerr bit are set, then the corresponding mob bit is set in the cansitn register. to acknowledge a mob interrupt, the corresponding bits of canstmob register (rxok, txok,...) must be cleared by the software app lication. this operation needs a read-modify-write software routine. to acknowledge a general interrupt, the correspon ding bits of cangit register (bxok, bof- fit,...) must be cleared by the software applicatio n. this operation is made writing a logical one in these interrupt flags (writing a logical zero doesn?t change the interrupt flag value). ovrtim interrupt flag is reset as the other interrupt sources of cangit register and is also reset entering in its dedicated interrupt handler. when the can node is in transmission and detects a form error in its fr ame, a bit error will also be raised. consequently, two co nsecutive interrupts can occur, both due to the same error. when a mob error occurs and is set in its own canstmob register, no general error is set in cangit register. txok[i] canstmob.6 rxok[i] canstmob.5 berr[i] canstmob.4 serr[i] canstmob.3 cerr[i] canstmob.2 ferr[i] canstmob.1 aerr[i] canstmob.0 bxok cangit.4 serg cangit.3 cerg cangit.2 ferg cangit.1 aerg cangit.0 boffi cangit.6 entx cangie.4 enrx cangie.5 enerr cangie.3 enbx cangie.2 energ cangie.1 enboff cangie.6 iemob[i] canie 1/2 enit cangie.7 enovrt cangie.0 sit[i] cansit 1/2 canit cangit.7 can it ovr it 0 i ovrtim cangit.5 251 7679h?can?08/08 at90can32/64/128 19.9 can register description figure 19-15. registers organization general control general status general interrupt bit timing 1 bit timing 2 bit timing 3 enable mob 2 enable mob 1 enable interrupt status interrupt mob 2 status interrupt mob 1 enable interrupt mob 2 enable interrupt mob 1 can timer control can ttc low can ttc high can timer low can timer high tec counter rec counter hightest priority mob page mob mob number data index id tag 2 id tag 1 id tag 4 id tag 3 id mask 2 id mask 1 id mask 4 id mask 3 time stamp low time stamp high message data mob status mob control & dlc page mob mob0 - id tag 2 mob0 - id tag 1 mob0 - id tag 4 mob0 - id tag 3 mob0 - id mask 2 mob0 - id mask 1 mob0 - id mask 4 mob0 - id mask 3 mob0 - time stamp low mob0 - time stamp high mob0 - mob status mob0 - mob ctrl & dlc mob0 - mess. data - byte 0 mob (i) - id tag 2 mob (i) - id tag 1 mob (i) - id tag 4 mob (i) - id tag 3 mob (i) - id mask 2 mob (i) - id mask 1 mob (i) - id mask 4 mob (i) - id mask 3 mob (i) - time stamp low mob (i) - time stamp high mob (i) - mob status mob (i) - mob ctrl & dlc mob (i) - mess. data - byte 0 (i+1) message objects 8 bytes a vr registers registers in pages 252 7679h?can?08/08 at90can32/64/128 19.10 general can registers 19.10.1 can general control register - cangcon ? bit 7 ? abrq: abort request this is not an auto resettable bit. ? 0 - no request. ? 1 - abort request: a reset of canen1 and canen2 registers is done. the pending communications are immediately disabled and the on-going one will be normally terminated, setting the appropriate status flags. note that cancdmob register remain unchanged. ? bit 6 ? ovrq: overload frame request this is not an auto resettable bit. ? 0 - no request. ? 1 - overload frame request: send an overload frame after the next received frame. the overload frame can be traced observing ovfg in cangsta register (c.f. figure 19-9 on page 243 ). ? bit 5 ? ttc: time trigger communication ? 0 - no ttc. ?1 - ttc mode. ? bit 4 ? synttc: synchronization of ttc this bit is only used in ttc mode. ? 0 - the ttc timer is caught on sof. ? 1 - the ttc timer is caught on the last bit of the eof. ? bit 3 ? listen: listening mode ? 0 - no listening mode. ? 1 - listening mode. ? bit 2 ? test: test mode ? 0 - no test mode ? 1 - test mode: intend for factory testing and not for customer use. note: can may ma lfunction if this bit is set. ? bit 1 ? ena/stb : enable / standby mode because this bit is a command and is not immedi ately effective, the enfg bit in cangsta reg- ister gives the true state of the chosen mode. bit 76543210 abrq ovrq ttc synttc listen test ena/stb swres cangcon read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 253 7679h?can?08/08 at90can32/64/128 ? 0 - standby mode: the on-going transmission (if exists) is normally terminated and the can channel is frozen (the conmob bits of every mob do not change). the transmitter constantly provides a recessive level. in this mode, the receiver is not enabled but all the registers and mailbox remain accessible from cpu. note: a standby mode applied during a reception may corrupt the on-going reception or set the controller in a wrong state. th e controller will restart correctly from this state if a software reset (swres) is applied. if no reset is considered, a possible solution is to wait for a lake of a receiver busy (rxbsy) before to enter in stand-b y mode. the best solution is first to apply an abort request command (abrq) and then wait for the lake of the receiver busy (rxbsy) before to enter in stand-by mode . in any cases, this standby mode behav- ior has no effect on the can bus integrity. ? 1 - enable mode: the can channel enters in enable mode once 11 recessive bits has been read. ? bit 0 ? swres: software reset request this auto resettable bit on ly resets the can controller. ?0 - no reset ? 1 - reset: this reset is ?ored? with the hardware reset. 19.10.2 can general stat us register - cangsta ? bit 7 ? reserved bit this bit is reserved for future use. ? bit 6 ? ovrg: overload frame flag this flag does not generate an interrupt. ? 0 - no overload frame. ? 1 - overload frame: set by hardware as l ong as the produced overload frame is sent. ? bit 5 ? reserved bit this bit is reserv ed for future use. ? bit 4 ? txbsy: transmitter busy this flag does not generate an interrupt. ? 0 - transmi tter not busy. ? 1 - transmitter busy: set by hardware as long as a frame (data, remote, overload or error frame) or an ack field is sent. al so set when an inter frame space is sent. ? bit 3 ? rxbsy: receiver busy this flag does not generate an interrupt. ? 0 - receiver not busy ? 1 - receiver busy: set by hardware as long as a frame is received or monitored. ? bit 2 ? enfg: enable flag bit 76543210 - ovrg - txbsy rxbsy enfg boff errp cangsta read/write - r - r r r r r initial value- 0 - 00000 254 7679h?can?08/08 at90can32/64/128 this flag does not generate an interrupt. ? 0 - can controller disable: because an enable/standby command is not immediately effective, this status gives the true state of the chosen mode. ? 1 - can controller enable. ? bit 1 ? boff: bus off mode boff gives the information of the state of the can channel. only entering in bus off mode gen- erates the boffit interrupt. ? 0 - no bus off mode. ? 1 - bus off mode. ? bit 0 ? errp: error passive mode errp gives the information of the state of the can channel. this flag does not generate an interrupt. ? 0 - no error passive mode. ? 1 - error passive mode. 19.10.3 can general inte rrupt register - cangit ? bit 7 ? canit: general interrupt flag this is a read only bit. ? 0 - no interrupt. ? 1 - can interrupt: image of all the can controller inte rrupts except for ovrtim interrupt. this bit can be used for polling method. ? bit 6 ? boffit: bus off interrupt flag writing a logical one resets this interrupt flag. boffit flag is only se t when the can enters in bus off mode (coming from error passive mode). ? 0 - no interrupt. ? 1 - bus off interrupt when the can enters in bus off mode. ? bit 5 ? ovrtim: overrun can timer writing a logical one resets this interrupt flag. entering in can timer overrun interrupt handler also reset this interrupt flag ? 0 - no interrupt. ? 1 - can timer overrun interrupt: set when the can timer switches from 0xffff to 0. ? bit 4 ? bxok: frame buffer receive interrupt writing a logical one resets this interrupt flag. bxok flag can be clear ed only if all conmob fields of the mob?s of the buffer have been re-written before. ? 0 - no interrupt. bit 76543210 canit boffit ovrtim bxok serg cerg ferg aerg cangit read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000000 255 7679h?can?08/08 at90can32/64/128 ? 1 - burst receive interrupt: set when the frame buffer receive is completed. ? bit 3 ? serg: stuff error general writing a logical one rese ts this interrupt flag. ? 0 - no interrupt. ? 1 - stuff error interrupt: detection of more than 5 consecutive bits with the same polarity. ? bit 2 ? cerg: crc error general writing a logical one rese ts this interrupt flag. ? 0 - no interrupt. ? 1 - crc error interrupt: the crc check on destuffed message does not fit with the crc field. ? bit 1 ? ferg: form error general writing a logical one rese ts this interrupt flag. ? 0 - no interrupt. ? 1 - form error interrupt: one or more violat ions of the fixed form in the crc delimiter, acknowledgment delimiter or eof. ? bit 0 ? aerg: acknowledgment error general writing a logical one rese ts this interrupt flag. ? 0 - no interrupt. ? 1 - acknowledgment error interrupt: no det ection of the dominant bit in acknowledge slot. 19.10.4 can general interrupt enable register - cangie ? bit 7 ? enit: enable all interrupts (except for can timer overrun interrupt) ? 0 - interrupt disabled. ? 1- canit interrupt enabled. ? bit 6 ? enboff: enable bus off interrupt ? 0 - interrupt disabled. ? 1- bus off interrupt enabled. ? bit 5 ? enrx: enable receive interrupt ? 0 - interrupt disabled. ? 1- receive interrupt enabled. ? bit 4 ? entx: enable transmit interrupt ? 0 - interrupt disabled. bit 76543210 enit enboff enrx entx enerr enbx energ enovrt cangie read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 256 7679h?can?08/08 at90can32/64/128 ? 1- transmit interrupt enabled. ? bit 3 ? enerr: enable mob errors interrupt ? 0 - interrupt disabled. ? 1- mob errors interrupt enabled. ? bit 2 ? enbx: enable frame buffer interrupt ? 0 - interrupt disabled. ? 1- frame buffer interrupt enabled. ? bit 1 ? energ: enable general errors interrupt ? 0 - interrupt disabled. ? 1- general errors interrupt enabled. ? bit 0 ? enovrt: enable can timer overrun interrupt ? 0 - interrupt disabled. ? 1- can timer interrupt overrun enabled. 19.10.5 can enable mob registers - canen2 and canen1 ? bits 14:0 - enmob14:0: enable mob this bit provides the availability of the mob. it is set to one when the mob is enable d (i.e. conmob1:0 of cancdmob register). once txok or rxok is set to one (txok for automatic reply), the corresponding enmob is reset. enmob is also set to zero configuring the mob in disabled mode, applying abortion or standby mode. ? 0 - message object disabled: mob available for a new transmission or reception. ? 1 - message object enabled: mob in use. ? bit 15 ? reserved bit this bit is reserv ed for future use. bit 76543210 enmob7 enmob6 enmob5 enmob4 en mob3 enmob2 enmob1 enmob0 canen2 - enmob14 enmob13 enmob12 enmob11 enmob10 enmob9 enmob8 canen1 bit 151413121110 9 8 read/write r r rrrrrr initial value00000000 read/write - r rrrrrr initial value-0000000 257 7679h?can?08/08 at90can32/64/128 19.10.6 can enable interrupt mob registers - canie2 and canie1 ? bits 14:0 - iemob14:0: interrupt enable by mob ? 0 - interrupt disabled. ? 1 - mob interrupt enabled note: example: canie2 = 0000 1100 b : enable of interrupts on mob 2 & 3. ? bit 15 ? reserved bit this bit is reserved for future us e. for compatibility with future devices, it mu st be written to zero when canie1 is written. 19.10.7 can status interrupt mob registers - cansit2 and cansit1 ? bits 14:0 - sit14:0: status of interrupt by mob ? 0 - no interrupt. ? 1- mob interrupt. note: example: cansit2 = 0010 0001 b : mob 0 & 5 interrupts. ? bit 15 ? reserved bit this bit is reserv ed for future use. 19.10.8 can bit timing register 1 - canbt1 ? bit 7? reserved bit this bit is reserved for future us e. for compatibility with future devices, it mu st be written to zero when canbt1 is written. ? bit 6:1 ? brp5:0: baud rate prescaler bit 76543210 iemob7 iemob6 iemob5 iemob4 ie mob3 iemob2 iemob1 iemob0 canie2 - iemob14 iemob13 iemob12 iemo b11 iemob10 iemob9 iemob8 canie1 bit 151413121110 9 8 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 read/write - r/w r/w r/w r/w r/w r/w r/w initial value- 0000000 bit 76543210 sit7 sit6 sit5 sit4 sit3 sit2 sit1 sit0 cansit2 - sit14 sit13 sit12 sit11 sit10 sit9 sit8 cansit1 bit 151413121110 9 8 read/write r r r r r r r r initial value00000000 read/write - r r r r r r r initial value- 0000000 bit 76543210 - brp5 brp4 brp3 brp2 brp1 brp0 - canbt1 read/write - r/w r/w r/w r/w r/w r/w - initial value- 000000 - 258 7679h?can?08/08 at90can32/64/128 the period of the can controller system clock t scl is programmable and determines the individ- ual bit timing. if brp[5..0]=0, see section 19.4.3 ?baud rate? on page 242 and section ? ?bit 0 ? smp: sample point(s)? on page 259 . ? bit 0 ? reserved bit this bit is reserved for future us e. for compatibility with future devices, it mu st be written to zero when canbt1 is written. 19.10.9 can bit timing register 2 - canbt2 ? bit 7? reserved bit this bit is reserved for future us e. for compatibility with future devices, it mu st be written to zero when canbt2 is written. ? bit 6:5 ? sjw1:0: re-synchronization jump width to compensate for pha se shifts between clock oscillators of different bus cont rollers, the control- ler must re-synchronize on any relevant signal edge of the current transmission. the synchronization jump width defines the maximum number of clock cycles. a bit period may be shortened or lengthened by a re-synchronization. ? bit 4 ? reserved bit this bit is reserved for future us e. for compatibility with future devices, it mu st be written to zero when canbt2 is written. ? bit 3:1 ? prs2:0: propagation time segment this part of the bit time is used to compensate for the physical delay times within the network. it is twice the sum of the signal propagation time on the bus line, the input comparator delay and the output driver delay. ? bit 0 ? reserved bit this bit is reserved for future us e. for compatibility with future devices, it mu st be written to zero when canbt2 is written. 19.10.10 can bit timing register 3 - canbt3 tscl = brp[5:0] + 1 clk io frequency bit 76543210 - sjw1 sjw0 - prs2 prs1 prs0 - canbt2 read/write - r/w r/w - r/w r/w r/w - initial value - 0 0 - 0 0 0 - tsjw = tscl x (sjw [1:0] +1) tprs = tscl x (prs [2:0] + 1) bit 76543210 - phs22 phs21 phs20 phs12 phs11 phs10 smp canbt3 read/write - r/w r/w r/w r/w r/w r/w r/w initial value- 0000000 259 7679h?can?08/08 at90can32/64/128 ? bit 7? reserved bit this bit is reserved for future us e. for compatibility with future devices, it mu st be written to zero when canbt3 is written. ? bit 6:4 ? phs22:0: phase segment 2 this phase is used to compensate for phase edge errors. this segment may be shortened by the re-synchronization jump width. phs2[2..0] shall be 1 and phs1[2..0] (c.f. section 19.2.3 ?can bit timing? on page 236 and section 19.4.3 ?baud rate? on page 242 ). ? bit 3:1 ? phs12:0: phase segment 1 this phase is used to compensate for phase edge errors. this segment may be lengthened by the re-synchronization jump width. ? bit 0 ? smp: sample point(s) this option allows to filter possible noise on txcan input pin. ? 0 - the sampling will occur once at the user configured sampling point - sp . ? 1 - with three-point sampling configur ation the first sampling will occur two t clk io clocks before the user configured sampling point - sp , again at one t clk io clock before sp and finally at sp . then the bit level will be determ ined by a majority vote of the three samples. ?smp=1? configuration is not compatible with ?brp[5:0]=0? because tq = t clk io . if brp = 0, smp must be cleared. 19.10.11 can timer control register - cantcon ? bit 7:0 ? tprsc7:0: can timer prescaler prescaler for the can timer upper counter range 0 to 255. it provides the clock to the can timer if the can controller is enabled. t clk cantim = t clk io x 8 x (cantcon [7:0] + 1) 19.10.12 can timer registers - cantiml and cantimh ? bits 15:0 - cantim15:0: can timer count can timer counter range 0 to 65,535. tphs2 = tscl x (phs2 [2:0] + 1) tphs1 = tscl x (phs1 [2:0] + 1) bit 76543210 tprsc7 tprsc6 tprsc5 tprsc4 tprs c3 tprsc2 trpsc1 tprsc0 cantcon read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit76543210 cantim7 cantim6 cantim5 cantim4 cantim3 cantim2 cantim1 cantim0 cantiml cantim15 cantim14 cantim13 cantim12 cantim11 cantim10 cantim9 cantim8 cantimh bit 1514131211109 8 read/writerrrrrrrr initial value00000000 260 7679h?can?08/08 at90can32/64/128 19.10.13 can ttc timer registers - canttcl and canttch ? bits 15:0 - timttc15:0: ttc timer count can ttc timer counter range 0 to 65,535. 19.10.14 can transmit error counter register - cantec ? bit 7:0 ? tec7:0: transmit error count can transmit error counter range 0 to 255. 19.10.15 can receive error counter register - canrec ? bit 7:0 ? rec7:0: receive error count can receive error counter range 0 to 255. 19.10.16 can highest priority mob register - canhpmob ? bit 7:4 ? hpmob3:0: highest priority mob number mob having the highest priority in cansit registers. if cansit = 0 (no mob), the return value is 0xf. note: do not confuse ?mob priority? and ?message id priority?. see ?message objects? on page 243. ? bit 3:0 ? cgp3:0: can general purpose bits these bits can be pre-programmed to match wi th the wanted configuration of the canpage register (i.e., ainc and indx2:0 setting). 19.10.17 can page mo b register - canpage bit 76543210 timttc7 timttc6 timttc5 timttc4 timttc3 timttc2 timttc1 timttc0 canttcl timttc15 timttc14 timttc13 timttc12 timttc11 timttc10 timttc9 timttc8 canttch bit 15141312111098 read/writerrrrrrrr initial value 0 0 0 0 0 0 0 0 bit 76543210 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 cantec read/write r r r r r r r r initial value00000000 bit 76543210 rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 canrec read/write r r r r r r r r initial value00000000 bit 76543210 hpmob3 hpmob2 hpmob1 hpmob0 cgp3 cgp 2cgp 1cgp 0 canhpmob read/write r r r r r/w r/w r/w r/w initial value 1 1 1 1 0 0 0 0 bit 76543210 mobnb3 mobnb2 mobnb1 mobnb0 ainc indx2 indx1 indx0 canpage read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 261 7679h?can?08/08 at90can32/64/128 ? bit 7:4 ? mobnb3:0: mob number selection of the mob number, the available numbers are from 0 to 14. ? bit 3 ? ainc : auto increment of the fifo can data buffer index (active low) ? 0 - auto increment of the index (default value). ? 1- no auto increment of the index. ? bit 2:0 ? indx2:0: fifo can data buffer index byte location of the can data byte into the fifo for the defined mob. 19.11 mob registers the mob registers has no initial (default) value after reset. 19.11.1 can mob status register - canstmob ? bit 7 ? dlcw: data length code warning the incoming message does not have the dlc expected. whatever the frame type, the dlc field of the cancdmob register is updated by the received dlc. ? bit 6 ? txok: transmit ok this flag can generate an interrupt. it must be cleared using a read-modify-write software routine on the whole canstmob register. the communication enabled by transmission is completed. txok rises at the end of eof field and then, the mob is disabled (the corresponding enmob-bit of canen registers is cleared). when the controll er is ready to send a frame, if two or more message objects are enabled as producers, the lower mob index is supplied first. ? bit 5 ? rxok: receive ok this flag can generate an interrupt. it must be cleared using a read-modify-write software routine on the whole canstmob register. the communication enabled by reception is completed. rxok rises at the end of the 6 th bit of eof field and then, the mob is disabled (the correspond- ing enmob-bit of canen registers is cleared). in case of two or more message object reception hits, the lower mob index is updated first. ? bit 4 ? berr: bit error (only in transmission) this flag can generate an interrupt. it must be cleared using a read-modify-write software routine on the whole canstmob register. the bit value monitored is different from the bit value sent. exceptions: the monitored recessive bit sent as a dominant bit during the arbitration field and the acknowledge slot detecting a dominant bit during the sending of an error frame. bit 76543210 dlcw txok rxok berr serr cerr ferr aerr canstmob read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value-------- 262 7679h?can?08/08 at90can32/64/128 the rising of this flag does not disable the mo b (the corresponding enmob-bit of canen regis- ters is not cleared). the next matc hing frame will update the berr flag. ? bit 3 ? serr: stuff error this flag can generate an interrupt. it must be cleared using a read-modify-write software routine on the whole canstmob register. detection of more than five consecutive bits with the same polarity. this flag can generate an interrupt. the rising of this flag does not disable the mo b (the corresponding enmob-bit of canen regis- ters is not cleared). the next matc hing frame will update the serr flag. ? bit 2 ? cerr: crc error this flag can generate an interrupt. it must be cleared using a read-modify-write software routine on the whole canstmob register. the receiver performs a crc check on every de-stuffed received mess age from the start of frame up to the data field. if this checking does not match with the de -stuffed crc field, a crc error is set. the rising of this flag does not disable the mo b (the corresponding enmob-bit of canen regis- ters is not cleared). the next matc hing frame will update the cerr flag. ? bit 1 ? ferr: form error this flag can generate an interrupt. it must be cleared using a read-modify-write software routine on the whole canstmob register. the form error results from one or more violatio ns of the fixed form in the following bit fields: ? crc delimiter. ? acknowledgment delimiter. ?eof the rising of this flag does not disable the mo b (the corresponding enmob-bit of canen regis- ters is not cleared). the next matchi ng frame will update the ferr flag. ? bit 0 ? aerr: acknowledgment error this flag can generate an interrupt. it must be cleared using a read-modify-write software routine on the whole canstmob register. no detection of the dominant bit in the acknowledge slot. the rising of this flag does not disable the mo b (the corresponding enmob-bit of canen regis- ters is not cleared). the next matc hing frame will update the aerr flag. 19.11.2 can mob control an d dlc register - cancdmob ? bit 7:6 ? conmob1:0: configuration of message object these bits set the communication to be performed ( no initial value after reset). bit 7 6 543210 conmob1 conmob0 rplv ide dlc3 dlc2 dlc1 dlc0 cancdmob read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value- - ------ 263 7679h?can?08/08 at90can32/64/128 ? 00 - disable. ? 01 - enable transmission. ? 10 - enable reception. ? 11 - enable frame buffer reception these bits are not cleared once the communication is performed. the user must re-write the configuration to enable a new communication. ? this operation is necessary to be able to reset the bxok flag. ? this operation also set the corresponding bit in the canen registers. ? bit 5 ? rplv: reply valid used in the automatic reply mode after receiving a remote frame. ? 0 - reply not ready. ? 1 - reply ready and valid. ? bit 4 ? ide: identifier extension ide bit of the remote or data frame to send. this bit is updated with the corresponding value of the remote or data frame received. ? 0 - can standard rev 2.0 a (identifiers length = 11 bits). ? 1 - can standard rev 2.0 b (identifiers length = 29 bits). ? bit 3:0 ? dlc3:0: data length code number of bytes in the data field of the message. dlc field of the remote or data frame to send. the range of dlc is from 0 up to 8. if dlc field >8 then effective dlc=8. this field is updated with the corresponding value of the remote or data frame received. if the expected dlc differs from the incoming dl c, a dlc warning appears in the canstmob register. 19.11.3 can identifier tag registers - canidt1, canidt2, canidt3, and canidt4 v2.0 part a v2.0 part b bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 - - - - - rtrtag - rb0tag canidt4 -------- canidt3 idt 2 idt 1 idt 0----- canidt2 idt 10 idt 9 idt 8 idt 7 idt 6 idt 5 idt 4 idt 3 canidt1 bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value-------- bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 idt 4 idt 3 idt 2 idt 1 idt 0 rtrtag rb1tag rb0tag canidt4 idt 12 idt 11 idt 10 idt 9 idt 8 idt 7 idt 6 idt 5 canidt3 idt 20 idt 19 idt 18 idt 17 idt 16 idt 15 idt 14 idt 13 canidt2 idt 28 idt 27 idt 26 idt 25 idt 24 idt 23 idt 22 idt 21 canidt1 264 7679h?can?08/08 at90can32/64/128 v2.0 part a ? bit 31:21 ? idt10:0: identifier tag identifier field of the remote or data frame to send. this field is updated with the corresponding value of the remote or data frame received. ? bit 20:3 ? reserved bits these bits are reserved for future use. for compatibility with future devices, they must be written to zero when canidtn are written. when a remote or data frame is received, these bits do not operate in the comparison but they are updated with un-predicted values. ? bit 2 ? rtrtag: remote transmission request tag rtr bit of the remote or data frame to send. this tag is updated with the corresponding value of the remote or data frame received. in case of automatic reply mode, this bit is automa tically reset before sending the response. ? bit 1 ? reserved bit this bit is reserved for future us e. for compatibility with future devices, it mu st be written to zero when canidtn are written. when a remote or data frame is received, this bit does not operate in the comparison but it is updated with un-predicted values. ? bit 0 ? rb0tag: reserved bit 0 tag rb0 bit of the remote or data frame to send. this tag is updated with the corresponding va lue of the remote or data frame received. v2.0 part b ? bit 31:3 ? idt28:0: identifier tag identifier field of the remote or data frame to send. this field is updated with the corresponding value of the remote or data frame received. ? bit 2 ? rtrtag: remote transmission request tag rtr bit of the remote or data frame to send. this tag is updated with the corresponding value of the remote or data frame received. in case of automatic reply mode, this bit is automa tically reset before sending the response. ? bit 1 ? rb1tag: reserved bit 1 tag rb1 bit of the remote or data frame to send. this tag is updated with the corresponding va lue of the remote or data frame received. bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value-------- 265 7679h?can?08/08 at90can32/64/128 ? bit 0 ? rb0tag: reserved bit 0 tag rb0 bit of the remote or data frame to send. this tag is updated with the corresponding va lue of the remote or data frame received. 19.11.4 can identifier mask registers - canidm1, canidm2, canidm3, and canidm4 v2.0 part a v2.0 part b v2.0 part a ? bit 31:21 ? idmsk10:0: identifier mask ? 0 - comparison true forced - see ?acceptance filter? on page 246. ? 1 - bit comparison enabled - see ?acceptance filter? on page 246. ? bit 20:3 ? reserved bits these bits are reserved for future use. for compatibility with future devices, they must be written to zero when canidmn are written. ? bit 2 ? rtrmsk: remote transmission request mask ? 0 - comparison true forced. ? 1 - bit comparison enabled. ? bit 1 ? reserved bit this bit is reserved for future us e. for compatibility with future devices, it mu st be written to zero when canidtn are written. ? bit 0 ? idemsk: identifier extension mask ? 0 - comparison true forced. ? 1 - bit comparison enabled. v2.0 part b bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 - - - - - rtrmsk - idemsk canidm4 -------- canidm3 idmsk 2 idmsk 1 idmsk 0----- canidm2 idmsk 10 idmsk 9 idmsk 8 idmsk 7 idmsk 6 idmsk 5 idmsk 4 idmsk 3 canidm1 bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value-------- bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 idmsk 4 idmsk 3 idmsk 2 idmsk 1 idmsk 0 rtrmsk - idemsk canidm4 idmsk 12 idmsk 11 idmsk 10 idmsk 9 idmsk 8 idmsk 7 idmsk 6 idmsk 5 canidm3 idmsk 20 idmsk 19 idmsk 18 idmsk 17 idmsk 16 idmsk 15 idmsk 14 idmsk 13 canidm2 idmsk 28 idmsk 27 idmsk 26 idmsk 25 idmsk 24 idmsk 23 idmsk 22 idmsk 21 canidm1 bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value-------- 266 7679h?can?08/08 at90can32/64/128 ? bit 31:3 ? idmsk28:0: identifier mask ? 0 - comparison true forced - see ?acceptance filter? on page 246. ? 1 - bit comparison enabled - see ?acceptance filter? on page 246. ? bit 2 ? rtrmsk: remote transmission request mask ? 0 - comparison true forced ? 1 - bit comparison enabled. ? bit 1 ? reserved bit writing zero in this bit is recommended. ? bit 0 ? idemsk: identifier extension mask ? 0 - comparison true forced ? 1 - bit comparison enabled. 19.11.5 can time stamp registers - canstml and canstmh ? bits 15:0 - timstm15:0: time stamp count can time stamp counter range 0 to 65,535. 19.11.6 can data message register - canmsg ? bit 7:0 ? msg7:0: message data this register contains the can data byte pointed at the page mob register. after writing in the page mob regist er, this byte is equal to the specified message location of the pre-defined identifier + index. if auto-incrementatio n is used, at the end of the data register writ- ing or reading cycle, the index is auto-incremented. the range of the counting is 8 with no end of loop (0, 1,..., 7, 0,...). 19.12 examples of can baud rate setting the can bus requires very accurate timing especi ally for high baud rates. it is recommended to use only an external crystal for can operations. (refer to ?bit timing? on page 241 and ?baud rate? on page 242 for timing description and page 257 to page 258 for ?can bit timing registers?). bit 76543210 timstm7 timstm6 timstm5 timstm4 timstm3 timstm2 timstm1 timstm0 canstml timstm15 timstm14 timstm13 timstm12 tims tm11 timstm10 timstm9 timstm8 canstmh bit 151413121110 9 8 read/write rrrrrrrr initial value-------- bit 76543210 msg 7 msg 6 msg 5 msg 4 msg 3 msg 2 msg 1 msg 0 canmsg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value-------- 267 7679h?can?08/08 at90can32/64/128 table 19-2. examples of can baud rate settings for commonly frequencies f clk io (mhz) can baudrate (kbps) description segments registers sampling point tq (s) tbit (tq) tprs (tq) tph1 (tq) tph2 (tq) tsjw (tq) canbt1 canbt2 canbt3 16.000 1000 69 % (1) 0.0625 16 7 4 4 1 0x00 0x0c 0x36 (2) 75 % 0.125 8 3 2 2 1 0x02 0x04 0x13 500 75 % 0.125 16 7 4 4 1 0x02 0x0c 0x37 0.250 8 3 2 2 1 0x06 0x04 0x13 250 75 % 0.250 16 7 4 4 1 0x06 0x0c 0x37 0.500 8 3 2 2 1 0x0e 0x04 0x13 200 75 % 0.3125 16 7 4 4 1 0x08 0x0c 0x37 0.625 8 3 2 2 1 0x12 0x04 0x13 125 75 % 0.500 16 7 4 4 1 0x0e 0x0c 0x37 1.000 8 3 2 2 1 0x1e 0x04 0x13 100 75 % 0.625 16 7 4 4 1 0x12 0x0c 0x37 1.250 8 3 2 2 1 0x26 0x04 0x13 12.000 1000 67 % (1) 0.083333 12 5 3 3 1 0x00 0x08 0x24 (2) x - - - n o d a t a - - - 500 75 % 0.166666 12 5 3 3 1 0x02 0x08 0x25 0.250 8 3 2 2 1 0x04 0x04 0x13 250 75 % 0.250 16 7 4 4 1 0x04 0x0c 0x37 0.500 8 3 2 2 1 0x0a 0x04 0x13 200 75 % 0.250 20 8 6 5 1 0x04 0x0e 0x4b 0.416666 12 5 3 3 1 0x08 0x08 0x25 125 75 % 0.500 16 7 4 4 1 0x0a 0x0c 0x37 1.000 8 3 2 2 1 0x16 0x04 0x13 100 75 % 0.500 20 8 6 5 1 0x0a 0x0e 0x4b 0.833333 12 5 3 3 1 0x12 0x08 0x25 268 7679h?can?08/08 at90can32/64/128 note: 1. see section 19.4.3 ?baud rate? on page 242 . 2. see section ? ?bit 0 ? smp: sample point(s)? on page 259 8.000 1000 63 % (1) x - - - n o d a t a - - - 0.125 8 3 2 2 1 0x00 0x04 0x12 (2) 500 69 % (1) 0.125 16 7 4 4 1 0x00 0x0c 0x36 (2) 75 % 0.250 8 3 2 2 1 0x02 0x04 0x13 250 75 % 0.250 16 7 4 4 1 0x02 0x0c 0x37 0.500 8 3 2 2 1 0x06 0x04 0x13 200 75 % 0.250 20 8 6 5 1 0x02 0x0e 0x4b 0.625 8 3 2 2 1 0x08 0x04 0x13 125 75 % 0.500 16 7 4 4 1 0x06 0x0c 0x37 1.000 8 3 2 2 1 0x0e 0x04 0x13 100 75 % 0.625 16 7 4 4 1 0x08 0x0c 0x37 1.250 8 3 2 2 1 0x12 0x04 0x13 6.000 1000 - - - n o t a p p l i c a b l e - - - 500 67 % (1) 0.166666 12 5 3 3 1 0x00 0x08 0x24 (2) x - - - n o d a t a - - - 250 75 % 0.333333 12 5 3 3 1 0x02 0x08 0x25 0.500 8 3 2 2 1 0x04 0x04 0x13 200 80 % 0.333333 15 7 4 3 1 0x02 0x0c 0x35 0.500 10 4 3 2 1 0x04 0x06 0x23 125 75 % 0.500 16 7 4 4 1 0x04 0x0c 0x37 1.000 8 3 2 2 1 0x0a 0x04 0x13 100 75 % 0.500 20 8 6 5 1 0x04 0x0e 0x4b 0.833333 12 5 3 3 1 0x08 0x08 0x25 4.000 1000 - - - n o t a p p l i c a b l e - - - 500 63 % (1) x - - - n o d a t a - - - 0.250 8 3 2 2 1 0x00 0x04 0x12 (2) 250 69 % (1) 0.250 16 7 4 4 1 0x00 0x0c 0x36 (2) 75 % 0.500 8 3 2 2 1 0x02 0x04 0x13 200 70 % (1) 0.250 20 8 6 5 1 0x00 0x0e 0x4a (2) x - - - n o d a t a - - - 125 75 % 0.500 16 7 4 4 1 0x02 0x0c 0x37 1.000 8 3 2 2 1 0x06 0x04 0x13 100 75 % 0.500 20 8 6 5 1 0x02 0x0e 0x4b 1.250 8 3 2 2 1 0x08 0x04 0x13 table 19-2. examples of can baud rate settings for commonly frequencies (continued) f clk io (mhz) can baudrate (kbps) description segments registers sampling point tq (s) tbit (tq) tprs (tq) tph1 (tq) tph2 (tq) tsjw (tq) canbt1 canbt2 canbt3 269 7679h?can?08/08 at90can32/64/128 20. analog comparator the analog comparator compares the input va lues on the positive pin ain0 and negative pin ain1. 20.1 overview when the voltage on the positive pin ain0 is higher than the voltage on the negative pin ain1, the analog comparator output, aco, is set. the comparator?s output can be set to trigger the timer/counter1 input capture function. in additio n, the comparator can trigger a separate inter- rupt, exclusive to the analog comparator. the user can select interrupt triggering on comparator output rise, fall or toggle. a block diagram of t he comparator and its surrounding logic is shown in figure 20-1 . figure 20-1. analog comparator block diagram (1)(2) notes: 1. adc multiplexer output: see table 20-2 on page 271 . 2. refer to figure 1-2 on page 5 or figure 1-3 on page 6 and table 9-15 on page 83 for analog comparator pin placement. 20.2 analog comparator register description 20.2.1 adc control and stat us register b ? adcsrb ? bit 6 ? acme: analog comparator multiplexer enable when this bit is written logic one and the adc is switched off (aden in adcsra is zero), the adc multiplexer selects the negative input to the analog comparator. when this bit is written logic zero, ain1 is applied to the negative input of the analog comparator. for a detailed description of this bit, see ?analog comparator multiplexed input? on page 271 . acbg bandgap reference adc multiplexer output acme aden t/c1 input capture bit 7 6543210 - acme ? ? ? adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value 0 0000000 270 7679h?can?08/08 at90can32/64/128 20.2.2 analog comparator control and status register ? acsr ? bit 7 ? acd: analog comparator disable when this bit is written logic one, the power to the analog comparator is switched off. this bit can be set at any time to tu rn off the analog com parator. this will reduce power consumption in active and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. ot herwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set, a fixed bandgap reference vo ltage replaces the positive input to the analog comparator. when this bit is clea red, ain0 is applied to the positive input of the analog compar- ator. see ?internal voltage reference? on page 56. ? bit 5 ? aco: analog comparator output the output of the analog comparator is synchron ized and then directly connected to aco. the synchronization introduces a delay of 1 - 2 clock cycles. ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers t he interrupt mode defined by acis1 and acis0. the analog comparator interr upt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when executing the corresponding inter- rupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i-bi t in the status register is set, the analog com- parator interrupt is activated. when writ ten logic zero, the interrupt is disabled. ? bit 2 ? acic: analog comparator input capture enable when written logic one, this bit enables the input ca pture function in timer/counter1 to be trig- gered by the analog comparator. the comparator outp ut is in this case directly connected to the input capture front-end logic, ma king the comparator utilize the noise canceler and edge select features of the timer/counter1 input capture interrupt. when written logic zero, no connection between the analog comparator and the input c apture function exists. to make the comparator trigger the timer/counter1 input capture interr upt, the icie1 bit in the timer interrupt mask register (timsk1) must be set. bit 76543210 acd acbg aco aci acie acic acis1 acis0 acsr read/write r/w r/w r r/w r/w r/w r/w r/w initial value00n/a00000 271 7679h?can?08/08 at90can32/64/128 ? bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which compar ator events that trigger the an alog comparator interrupt. the different settings are shown in table 20-1 . when changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the acsr re gister. otherwise an interrupt can occur when the bits are changed. 20.3 analog comparator multiplexed input it is possible to select any of the adc7..0 pins to replace the negative input to the analog com- parator. the adc multiplexer is used to select this input, and conseq uently, the adc must be switched off to utilize this feature. if the analog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is switched off (a den in adcsra is zero), mux2..0 in admux select the input pin to replace the negative input to the analog comparator, as shown in table 20-2 . if acme is cleared or aden is set, ain1 is applied to the negative input to the analog comparator. table 20-1. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. table 20-2. analog comparator multiplexed input acme aden mux2..0 analog comparator negative input 0 x xxx ain1 1 1 xxx ain1 10 000adc0 10 001adc1 10 010adc2 10 011adc3 10 100adc4 10 101adc5 10 110adc6 10 111adc7 272 7679h?can?08/08 at90can32/64/128 20.3.1 digital input disa ble register 1 ? didr1 ? bit 1, 0 ? ain1d, ain0d: ai n1, ain0 digital input disable when this bit is written logic one, the digital inpu t buffer on the ain1/0 pin is disabled. the corre- sponding pin register bit will alwa ys read as zero when this bit is set. when an analog signal is applied to the ain1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. bit 76543210 ? ? ? ? ? ? ain1d ain0d didr1 read/write r r r r r r r/w r/w initial value00000000 273 7679h?can?08/08 at90can32/64/128 21. analog to digital converter - adc 21.1 features ? 10-bit resolution ? 0.5 lsb integral non-linearity ? 2 lsb absolute accuracy ? 65 - 260 s conversion time ? up to 15 ksps at maximum resolution ? eight multiplexed single ended input channels ? seven differential input channels ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 2.56 v adc reference voltage ? free running or single conversion mode ? adc start conversion by auto tr iggering on interrupt sources ? interrupt on adc conversion complete ? sleep mode noise canceler the at90can32/64/128 features a 10-bit succ essive approximation adc. the adc is con- nected to an 8-channel analog multiplexer which allows eigh t single-ended voltage inputs constructed from the pins of port f. the si ngle-ended voltage input s refer to 0v (gnd). the device also supports 16 differential voltage input combinations. two of the differential inputs (adc1, adc0 and adc3, adc2) are equipped wi th a programmable gain stage, providing amplification steps of 0 db (1x), 20 db (10x), or 46 db (200x) on the differential input voltage before the a/d conversion. seven differential analog input channels share a common negative terminal (adc1), while any other adc input can be selected as the positive input terminal. if 1x or 10x gain is used, 8-bit resolution can be expec ted. if 200x gain is used, 7-bit resolution can be expected. the adc contains a sample and hold circuit whic h ensures that the input voltage to the adc is held at a constant level during conversion . a block diagram of the adc is shown in figure 21-1 . the adc has a separate anal og supply voltage pin, av cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 280 on how to connect this pin. internal reference voltages of nominally 2.56v or av cc are provided on-chip. the voltage refer- ence may be externally decoupled at the aref pi n by a capacitor for be tter noise performance. 274 7679h?can?08/08 at90can32/64/128 figure 21-1. analog to digital converter block schematic 21.2 operation the adc converts an analog input voltage to a 10-bit digital value through successive approxi- mation. the minimum value represents gnd and the maximum value represents the voltage on adc conversion complete irq 8-bit data bus 15 0 adc mul tiplexer select (admux) adc ctrl. & st atus register (adcsra) adc data register (adch/adcl) mux2 adie adate adsc aden adif adif mux1 mux0 adps0 adps1 adps2 mux3 conversion logic 10-bit dac + - sample & hold comparator internal reference mux decoder mux4 avcc adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 refs0 refs1 adlar + - channel selection gain selection adc[9:0] adc multiplexer output differential amplifier aref bandgap reference prescaler single ended / differential selection gnd pos. input mux neg. input mux trigger select adts[2:0] interrupt flags start 275 7679h?can?08/08 at90can32/64/128 the aref pin minus 1 lsb. optionally, av cc or an internal 2.56v reference voltage may be con- nected to the aref pin by writing to the refsn bits in the admux register. the internal voltage reference may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel and diff erential gain are selected by writing to the mux bits in admux. any of the adc input pins, as well as gnd and a fixed bandgap voltage reference, can be selected as single ended inputs to the adc. a selection of adc input pins can be selected as positive and negative inputs to the differential amplifier. the adc is enabled by setting the adc enable bit, aden in adcsra. voltage reference and input channel selections will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommende d to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is pr esented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch, to ensure that t he content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result fr om the conversion is lost. when adch is read, adc access to the adch and ad cl registers is re-enabled. the adc has its own interrupt which can be tr iggered when a conversion completes. the adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if the result is lost. 21.3 starting a conversion a single conversion is started by writing a l ogical one to the adc start conversion bit, adsc. this bit stays high as long as the conversi on is in progress and will be cleared by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will finish the current conv ersion before performing the channel change. alternatively, a conversion can be triggered auto matically by various sour ces. auto triggering is enabled by setting the adc auto trigger enable bi t, adate in adcsra. the trigger source is selected by setting the adc trig ger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is st arted. this provides a method of starting con- versions at fixed intervals. if th e trigger signal is still set when the conversion completes, a new conversion will not be started. if another positive edge occurs on the trigger signal during con- version, the edge will be ignored. note that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enab le bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 276 7679h?can?08/08 at90can32/64/128 figure 21-2. adc auto trigger logic using the adc interrupt flag as a trigger sour ce makes the adc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, con- stantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcs ra. in this mode the adc will perform successive conversions independently of whether the a dc interrupt flag, adif is cleared or not. if auto triggering is enabled, single conversi ons can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progress. the adsc bit will be read as one during a conversion, independe ntly of how the conversion was started. 21.4 prescaling and conversion timing figure 21-3. adc prescaler by default, the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz to get maximum resolution. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 200 khz to get a higher sample rate. the adc module contains a prescaler, which generates an acceptab le adc clock frequency from any cpu frequency above 100 khz. the presca ling is set by the adps bits in adcsra. the prescaler starts counting from the moment th e adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start 277 7679h?can?08/08 at90can32/64/128 when initiating a single ended conversion by se tting the adsc bit in adcsra, the conversion starts at the following rising edge of the adc clock cycle. see ?differential channels? on page 278 for details on different ial conversion timing. a normal conversion takes 13 adc clock cycles. the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the analog circuitry. the actual sample-and-hold takes place 1.5 adc cl ock cycles after the start of a normal conver- sion and 13.5 adc clock cycles after the start of an first conversion. when a conversion is complete, the result is written to the adc data re gisters, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be init iated on the first rising adc clock edge. when auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-and-hold takes place two adc clock cycles after the rising edge on the tr igger source signal. three addi- tional cpu clock cycles are used for synchronization logic. in free running mode, a new conversion will be started immediately af ter the conversion com- pletes, while adsc remains high. for a summary of conversion times, see table 21-1 . figure 21-4. adc timing diagram, first conver sion (single conversion mode) figure 21-5. adc timing diagram, single conversion sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and refs update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 278 7679h?can?08/08 at90can32/64/128 figure 21-6. adc timing diagram, auto triggered conversion figure 21-7. adc timing diagram, free running conversion 21.4.1 differential channels when using differential channels, certain aspe cts of the conversion need to be taken into consideration. differential conversions are synchronized to the internal clock ck adc2 equal to half the adc clock frequency. this synchroniza tion is done automatically by the adc interface in such a way that the sample-and-hold occurs at a specific phase of ck adc2 . a conversion initiated by the user (i.e., all single conversions, and the first free running conversion) when ck adc2 is low will take the same amount of time as a single ended conversion (1 3 adc clock cycles from the next prescaled clock cycle). a conversion initiated by the user when ck adc2 is high will take 14 adc clock cycles due to the synchronization mechanism. in free running mode, a new conversion is table 21-1. adc conversion time condition first conversion normal conversion, single ended auto triggered conversion sample & hold (cycles from start of convention) 14.5 1.5 2 conversion time (cycles) 25 13 13.5 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock trigger source adif adch adcl cycle number 12 one conversion next conversion conversion complete prescaler reset adate prescaler reset sample & hold mux and refs update 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux and refs update 279 7679h?can?08/08 at90can32/64/128 initiated immediately after the previous conversion completes, and since ck adc2 is high at this time, all automatically started (i.e., all but the first) free running conversions will take 14 adc clock cycles. if differential channels are used and conversions are started by auto triggering, the adc must be switched off between conversions. when auto triggering is used, the adc prescaler is reset before the conversion is started. since the stage is dependent of a stable adc clock prior to the conversion, this conversion w ill not be valid. by disabling a nd then re-enabling the adc between each conversion (writing aden in adcsra to ?0? then to ?1?), only extended conversions are performed. the result from the extended conversions will be valid. see ?prescaling and conver- sion timing? on page 276 for timing details. the gain stage is optimized for a bandwidth of 4 kh z at all gain settings. higher frequencies may be subjected to non-linear amplification. an exte rnal low-pass filter should be used if the input signal contains higher frequency components th an the gain stage bandwidth. note that the adc clock frequency is independent of the gain stage bandwidth limitation. e.g. the adc clock period may be 6 s, allowing a channel to be sampled at 12 ksps, regardless of the bandwidth of this channel. 21.5 changing channel or reference selection the muxn and refs1:0 bits in the admux regi ster are single buffered through a temporary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point dur ing the conversion. the channel and reference selection is continuously updated until a conversion is started. once the conversion starts, the channel and reference selection is locked to ensu re a sufficient sampling time for the adc. con- tinuous updating resumes in the last adc cloc k cycle before the conversion completes (adif in adcsra is set). note that the conversion star ts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or reference selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of t he triggering event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion will be affected by the new settings. if both adate and aden is writ ten to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: 1. when adate or aden is cleared. 2. during conversion, minimum one adc clock cycle after the trigger event. 3. after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next adc conversion. special care should be taken when changing differential channels. once a differential channel has been selected, the stage may take as much as 125 s to stabilize to the new value. thus conversions should not be started within the first 125 s after selecting a new differential chan- nel. alternatively, conversion results obt ained within this period should be discarded. the same settling time should be observed for th e first differential conversion after changing adc reference (by changing the refs1:0 bits in admux). 280 7679h?can?08/08 at90can32/64/128 21.5.1 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: ? in single conversion mode, always select the channel before starting the conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. ? in free running mode, always select the chan nel before starting the first conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel selection. since the next conversion has already started automatically, the next result will reflect the previous channel selectio n. subsequent conversi ons will reflect the new channel selection. when switching to a differential gain channel, t he first conversion result may have a poor accu- racy due to the required settling time for the automatic offset cancellation circuitry. the user should preferably disregard the first conversion result. 21.5.2 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in code s close to 0x3ff. v ref can be selected as either av cc , internal 2.56v reference, or external aref pin. av cc is connected to the adc through a passive switch. the internal 2.56v reference is gener- ated from the internal bandgap reference (v bg ) through an internal amplifier. in either case, the external aref pin is directly connected to the adc, and the reference voltage can be made more immune to noise by connecting a capaci tor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedant voltmeter. note that v ref is a high impedant source, and only a capacitive load should be connected in a system. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the ap plication, as they will be shorte d to the external voltage. if no external voltage is applied to the aref pin, the user may switch between av cc and 2.56v as reference selection. the first adc conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. if differential channels are used, the sele cted reference should not be closer to av cc than indi- cated in table 26-6 on page 374 . 21.6 adc noise canceler the adc features a noise canceler that enables conversion during sleep mode to reduce noise induced from the cpu core and other i/o peripher als. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: 1. make sure that the adc is enabled and is not busy converti ng. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. 2. enter adc noise reduction mo de (or idle mode). the adc will start a conversion once the cpu has been halted. 3. if no other interrupts occur before the a dc conversion completes, the adc interrupt will wake up the cpu and execute the adc co nversion complete in terrupt routine. if 281 7679h?can?08/08 at90can32/64/128 another interrupt wakes up the cpu before the adc conversion is complete, that inter- rupt will be executed, and an adc conversion complete interrupt r equest will be generated when the adc conver sion completes. the cpu will remain in active mode until a new sleep command is executed. note that the adc will no t be automatically turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before enter- ing such sleep modes to avoid excessive power consumption. if the adc is enabled in such sleep modes and the user wants to perform differential conver- sions, the user is advised to switch the adc o ff and on after waking up from sleep to prompt an extended conversion to get a valid result. 21.6.1 analog input circuitry the analog input circuitry for single ended channels is illustrated in figure 21-8. an analog source applied to adcn is subjected to the pin capacitance and input leak age of that pin, regard- less of whether that channel is selected as input for the adc. when the channel is selected, the source must drive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals wit h an output impedance of approximately 10 k or less. if such a source is used, the sampling time will be negligible. if a source with higher imped- ance is used, the sampling time will depend on how long time the source nee ds to charge the s/h capacitor, with can vary widely. the user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the s/h capacitor. if differential gain channels are used, the input circuitry looks somewhat different, although source impedances of a few hundred k or less is recommended. signal components higher th an the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpr edictable signal convolution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. figure 21-8. analog input circuitry 21.6.2 analog noise canceling techniques digital circuitry inside and outside the device ge nerates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: adcn i ih c s/h = 14 pf v cc /2 i il 1..100 ko 282 7679h?can?08/08 at90can32/64/128 1. keep analog signal paths as short as possibl e. make sure analog tracks run over the analog ground plane, and keep them well aw ay from high-speed switching digital tracks. 2. the av cc pin on the device should be connected to the digital v cc supply voltage via an lc network as shown in figure 21-9 . 3. use the adc noise canceler function to reduce induced noise from the cpu. 4. if any adc port pins are used as digital outp uts, it is essential t hat these do not switch while a conversion is in progress. figure 21-9. adc power connections 21.6.3 offset compensation schemes the gain stage has a built-in offset cancellation circuitry that null s the offset of differential mea- surements as much as possible. the remainin g offset in the analog path can be measured directly by selecting the same channel for both di fferential inputs. this offset residue can be then subtracted in software from the measurement results. using this kind of software based offset correction, offset on any channel can be reduced below one lsb. 21.6.4 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0 x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. vcc gnd 100nf analog ground plane (adc0) pf0 (adc7) pf7 (adc1) pf1 (adc2) pf2 (adc3) pf3 (adc4) pf4 (adc5) pf5 (adc6) pf6 aref gnd avcc 52 53 54 55 56 57 58 59 60 61 61 62 62 63 63 64 64 1 51 nc (ad0) pa0 10uh 283 7679h?can?08/08 at90can32/64/128 figure 21-10. offset error ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 21-11. gain error ? integral non-linearity (inl): afte r adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. output code v ref input voltage ideal adc actual adc offset error output code v ref input voltage ideal adc actual adc gain error 284 7679h?can?08/08 at90can32/64/128 figure 21-12. integral non-linearity (inl) ? differential non-linearity (dnl): the maximum deviation of the actu al code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. figure 21-13. differential non-linearity (dnl) ? quantization error: due to the quantization of th e input voltage into a finite number of codes, a range of input volt ages (1 lsb wide) will code to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. th is is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. 21.7 adc conversion result after the conversion is complete (adif is high ), the conversion result can be found in the adc result registers (adcl, adch). output code v ref input voltage ideal adc actual adc inl output code 0x3ff 0x000 0 v ref input voltage dnl 1 lsb 285 7679h?can?08/08 at90can32/64/128 for single ended conversion, the result is: where v in is the voltage on the se lected input pin and v ref the selected voltage reference (see table 21-3 on page 287 and table 21-4 on page 288 ). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage minus one lsb. if differential channels are used, the result is: where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, gain the selected gain factor and v ref the selected voltage reference. the result is presented in two?s complement form, from 0x200 (-512d) through 0x1ff (+511d). note that if the user wants to perform a quick polarity check of the result , it is sufficient to re ad the msb of the result (adc9 in adch). if the bit is one, th e result is negative, and if this bit is zero, the result is posi- tive. figure 21-14 shows the decoding of the differential input range. table 82 shows the resulting output codes if the differential input channel pair (adcn - adcm) is selected with a reference voltage of v ref . figure 21-14. differential measurement range adc v in 1023 ? v ref -------------------------- = adc v pos v neg ? () gain 512 ?? v ref ------------------------------------------------------------------------ = 0 output code 0x1ff 0x000 v ref differential input voltage (volts) 0x3ff 0x200 - v ref 286 7679h?can?08/08 at90can32/64/128 example 1: ? admux = 0xed (adc3 - adc2, 10x gain, 2. 56v reference, left adjusted result) ? voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. ? adcr = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 ? adcl will thus read 0x00, and adch will read 0x9c. writing zero to adlar right adjusts the result: adcl = 0x70, adch = 0x02. example 2: ? admux = 0xfb (adc3 - adc2, 1x gain, 2.56v reference, left adjusted result) ? voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. ? adcr = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029 . ? adcl will thus read 0x40, and adch will read 0x0a. writing zero to adlar right adjusts the result: adcl = 0x00, adch = 0x29. table 21-2. correlation between input voltage and output codes v adcn read code corresponding decimal value v adcm + v ref /gain 0x1ff 511 v adcm + 0.999 v ref /gain 0x1ff 511 v adcm + 0.998 v ref /gain 0x1fe 510 ... ... ... v adcm + 0.001 v ref /gain 0x001 1 v adcm 0x000 0 v adcm - 0.001 v ref /gain 0x3ff -1 ... ... ... v adcm - 0.999 v ref /gain 0x201 -511 v adcm - v ref /gain 0x200 -512 287 7679h?can?08/08 at90can32/64/128 21.8 adc register description 21.8.1 adc multiplexer selection register ? admux ? bit 7:6 ? refs1:0: reference selection bits these bits select the voltage reference for the adc, as shown in table 21-3 . if these bits are changed during a conversion, the change will not go in effect until this conversion is complete (adif in adcsra is set). the internal voltage re ference options may not be used if an external reference voltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data register. write one to adlar to left adjust the result. otherw ise, the result is right adjusted. changing the adlar bit will affect t he adc data register immediately, regardless of any ongoing conver- sions. for a complete description of this bit, see ?the adc data register ? adcl and adch? on page 290 . ? bits 4:0 ? mux4:0: analog channel selection bits the value of these bits selects which combinatio n of analog inputs are connected to the adc. these bits also select the gain for the differential channels. see table 21-4 for details. if these bits are changed during a conversion, the change wil l not go in effect until this conversion is complete (adif in adcsra is set). bit 76543210 refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 21-3. voltage reference selections for adc refs1 refs0 voltage re ference selection 0 0 aref, internal vref turned off 01av cc with external capacitor on aref pin 10reserved 1 1 internal 2.56v voltage reference with external capacitor on aref pin 288 7679h?can?08/08 at90can32/64/128 table 21-4. input channel and gain selections mux4..0 single ended input positive differential input negative differential input gain 00000 adc0 n/a 00001 adc1 00010 adc2 00011 adc3 00100 adc4 00101 adc5 00110 adc6 00111 adc7 01000 n/a (adc0 / adc0 / 10x) 01001 adc1 adc0 10x 01010 (adc0 / adc0 / 200x) 01011 adc1 adc0 200x 01100 (adc2 / adc2 / 10x) 01101 adc3 adc2 10x 01110 (adc2 / adc2 / 200x) 01111 adc3 adc2 200x 10000 adc0 adc1 1x 10001 (adc1 / adc1 / 1x) 10010 adc2 adc1 1x 10011 adc3 adc1 1x 10100 adc4 adc1 1x 10101 adc5 adc1 1x 10110 adc6 adc1 1x 10111 adc7 adc1 1x 11000 adc0 adc2 1x 11001 adc1 adc2 1x 11010 (adc2 / adc2 / 1x) 11011 adc3 adc2 1x 11100 adc4 adc2 1x 11101 adc5 adc2 1x 11110 1.1v (v band gap ) n/a 11111 0v (gnd) 289 7679h?can?08/08 at90can32/64/128 21.8.2 adc control and stat us register a ? adcsra ? bit 7 ? aden: adc enable writing this bit to one enables the adc. by writi ng it to zero, the adc is turned off. turning the adc off while a conversion is in prog ress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free running mode, write this bit to one to start the first conversion. the first conversion after adsc has been written after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, will take 25 adc clock cycles instead of the norma l 13. this first conversi on performs initializa- tion of the adc. adsc will read as one as long as a conversion is in progress. when the co nversion is complete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is written to on e, auto triggering of the adc is enabled. the adc will start a con- version on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i-bit in sreg are set. adif is cleared by hardware when executing th e corresponding interrupt handling vector. alter- natively, adif is cleared by writ ing a logical one to the flag. beware that if doing a read-modify- write on adcsra, a pending interrupt can be dis abled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is written to one and the i-bit in sreg is set, the adc conversion complete inter- rupt is activated. bit 76543210 aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 290 7679h?can?08/08 at90can32/64/128 ? bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the division factor betwe en the xtal frequency and the input clock to the adc. 21.8.3 the adc data register ? adcl and adch adlar = 0 adlar = 1 when an adc conversion is complete, the result is found in these two registers. if differential channels are used, the result is presented in two?s complement form. when adcl is read, the adc data register is not updated unt il adch is read. consequently, if the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read adch. otherwis e, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adla r is cleared (default), the result is right adjusted. table 21-5. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 bit 151413121110 9 8 ? ? ? ? ? ? adc9 adc8 adch adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl bit 76543210 read/write rrrrrrrr rrrrrrrr initial value00000000 00000000 bit 151413121110 9 8 adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch adc1 adc0 ? ????? adcl bit 76543210 read/write rrrrrrrr rrrrrrrr initial value00000000 00000000 291 7679h?can?08/08 at90can32/64/128 ? adc9:0: adc conversion result these bits represent the result fr om the conversion, as detailed in ?adc conversion result? on page 284 . 21.8.4 adc control and stat us register b ? adcsrb ? bit 7? reserved bit this bit is reserved for future us e. for compatibility with future devices, it mu st be written to zero when adcsrb is written. ? bit 5:3? reserved bits these bits are reserved for future use. for compatibility with future devices, they must be written to zero when adcsrb is written. ? bit 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is written to one, the value of these bits selects which source will trigger an adc conversion. if adate is cleared, the adts2:0 settings will have no effect. a conversion will be triggered by the rising edge of the selected inte rrupt flag. note that switching from a trig- ger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. if aden in adcsra is set, this will start a conversion. switching to free running mode (adts[2:0]=0) will not cause a trigger event, even if t he adc interrupt flag is set . bit 76543210 ? acme ? ? ? adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 21-6. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event 292 7679h?can?08/08 at90can32/64/128 21.8.5 digital input disa ble register 0 ? didr0 ? bit 7:0 ? adc7d..adc0d: ad c7:0 digital input disable when this bit is written logic one, the digita l input buffer on the corresponding adc pin is dis- abled. the corresponding pin regist er bit will always read as zero when this bit is set. when an analog signal is applied to the adc7..0 pin and th e digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. bit 76543210 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 293 7679h?can?08/08 at90can32/64/128 22. jtag interface and on-chip debug system 22.1 features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the ieee std. 1149.1 (jtag) standard ? debugger access to: ? all internal peripheral units ? internal and external ram ? the internal register file ?program counter ? eeprom and flash memories ? extensive on-chip debug support for break conditions, including ? avr break instruction ? break on change of program memory flow ? single step break ? program memory break points on single address or address range ? data memory break points on single address or address range ? programming of flash, eeprom , fuses, and lock bits th rough the jtag interface ? on-chip debugging supported by avr studio ? 22.2 overview the avr ieee std. 1149.1 compliant jtag interface can be used for: ? testing pcbs by using the jtag boundary-scan capability ? programming the non-volatile memories, fuses and lock bits ? on-chip debugging a brief description is given in the following se ctions. detailed descriptions for programming via the jtag interface, and using the boundar y-scan chain can be found in the sections ?jtag programming overview? on page 352 and ?boundary-scan ieee 1149.1 (jtag)? on page 300 , respectively. the on-chip debug support is considered being private jtag instructions, and dis- tributed within atmel and to selected third party vendors only. figure 22-1 shows a block diagram of the jtag interface and the on-chip debug system. the tap controller is a state machine controlled by the tck and tms signals. the tap controller selects either the jtag instruction register or one of several data registers as the scan chain (shift register) between the tdi ? input and tdo ? output. the instruction register holds jtag instructions controlling the be havior of a data register. the id-register (identifier register), bypass register, and the boundary-scan chain are the data registers used for board-level testing. t he jtag programming interface (actually consist- ing of several physical and virtual data regist ers) is used for serial programming via the jtag interface. the internal scan chain and break point scan chain are used for on-chip debugging only. 22.3 test access port ? tap the jtag interface is accessed through four of the avr?s pins. in jtag terminology, these pins constitute the test access port ? tap. these pins are: ? tms : test mode select. this pin is used for navigating through the tap-controller state machine. 294 7679h?can?08/08 at90can32/64/128 ? tck : test clock. jtag operatio n is synchronous to tck. ? tdi : test data in. serial input data to be shifted in to the instruction register or data register (scan chains). ? tdo : test data out. serial output data from instruction register or data register (scan chains). the ieee std. 1149.1 also specif ies an optional tap signal; trst ? test reset ? which is not provided. when the jtagen fuse is unprogrammed, thes e four tap pins are normal port pins and the tap controller is in reset. wh en programmed and the jtd bit in mcucr is cleared, the tap input signals are internally pulled high and the jtag is enabled for boundary-scan and program- ming. in this case, the tap output pin (tdo) is left floating in states where the jtag tap controller is not shifting data, and must theref ore be connected to a pull-up resistor or other hardware having pull-ups (for instance the tdi-input of the next device in the scan chain). the device is shipped with this fuse programmed. for the on-chip debug system, in addition to the jtag interface pins, the reset pin is moni- tored by the debugger to be able to detect ex ternal reset sources. the debugger can also pull the reset pin low to reset the whole system, assumi ng only open collectors on the reset line are used in the application. 295 7679h?can?08/08 at90can32/64/128 figure 22-1. block diagram tap controller tdi tdo tck tms flash memory avr cpu digital peripheral units jtag / avr core communication interface breakpoint unit flow control unit ocd status and control internal scan chain m u x instruction register id register bypass register jtag programming interface pc instruction address data breakpoint scan chain address decoder analog peripherial units i/o port 0 i/o port n boundary scan chain analog inputs control & clock lines device boundary 296 7679h?can?08/08 at90can32/64/128 figure 22-2. tap controller state diagram 22.4 tap controller the tap controller is a 16-state finite state mach ine that controls the operation of the boundary- scan circuitry, jtag programmi ng circuitry, or on-chip debug system. the state transitions depicted in figure 22-2 depend on the signal present on tm s (shown adjacent to each state transition) at the time of the ri sing edge at tck. the initial stat e after a power-on reset is test- logic-reset. as a definition in this document, the lsb is shifted in and out first for all shift registers. assuming run-test/idle is the present state, a ty pical scenario for using the jtag interface is: ? at the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of tck to enter the shift instruction register ? sh ift-ir state. while in this state, shift the four bits of the jtag instructions into the jt ag instruction register from the tdi input at the rising edge of tck. the tms input must be held low during input of the 3 lsbs in order to remain in the shift-ir state. the msb of the instructi on is shifted in when this state is left by setting tms high. while the instruction is shifted in from the tdi pin, the captured ir-state 0x01 is shifted out on the tdo pin. the jtag instruction selects a par ticular data register as path between tdi and tdo and controls the circuitry surrounding the selected data register. test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 297 7679h?can?08/08 at90can32/64/128 ? apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. the instruction is latched onto the parallel output from the shift register path in the update-i r state. the exit-ir, pause-ir, and exit2-ir states are only used for navigating the state machine. ? at the tms input, apply the sequence 1, 0, 0 at the rising edges of tck to enter the shift data register ? shift-dr st ate. while in this state, upload t he selected data register (selected by the present jtag instruction in the jtag in struction register) from the tdi input at the rising edge of tck. in order to remain in the shift-dr state, the tms input must be held low during input of all bits except the msb. the msb of the data is shifted in when this state is left by setting tms high. while the data register is shifted in from the tdi pin, the parallel inputs to the data register captured in the capture-dr state is shifted out on the tdo pin. ? apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. if the selected data register has a latched parallel-output, the latching takes place in the update-dr state. the exit-dr, pause-dr, and exit2-dr states ar e only used for navigating the state machine. as shown in the state diagram, the run-tes t/idle state need not be entered between selecting jtag instruction and using data registers, and so me jtag instructions may select certain func- tions to be performed in the run-test/idle, making it unsuitable as an idle state. note: independent of the initial state of the tap c ontroller, the test-logic-reset state can always be entered by holding tms high for five tck clock periods. for detailed information on the jtag specif ication, refer to the literature listed in ?bibliography? on page 299 . 22.5 using the boundary-scan chain a complete description of the boundary-scan capabilities are given in the section ?boundary- scan ieee 1149.1 (jtag)? on page 300 . 22.6 using the on-c hip debug system as shown in figure 22-1 , the hardware support for on-chip debugging consists mainly of ? a scan chain on the interface between the internal avr cpu and the internal peripheral units. ? break point unit. ? communication interface between the cpu and jtag system. all read or modify/write operations needed for implementing the debugger are done by applying avr instructions via the internal avr cpu scan chain. the cpu sends the result to an i/o memory mapped location which is part of the communication interface between the cpu and the jtag system. the break point unit implements break on change of program flow, single step break, two program memory break points, and two combined break points. together, the four break points can be configured as either: ? 4 single program memory break points. ? 3 single program memory break points + 1 single data memory break point. ? 2 single program memory break points + 2 single data memory break points. 298 7679h?can?08/08 at90can32/64/128 ? 2 single program memory break points + 1 program memory break point with mask (?range break point?). ? 2 single program memory break points + 1 data memory break point with mask (?range break point?). a debugger, like the avr studio, may however use one or more of these resources for its inter- nal purpose, leaving less flexibility to the end-user. a list of the on-chip debug specific jtag instructions is given in ?on-chip debug specific jtag instructions? on page 298 . the jtagen fuse must be programmed to enable the jtag test access port. in addition, the ocden fuse must be programmed and no lock bits must be set for the on-chip debug system to work. as a security feature, the on-chip debug system is disabled when either of the lb1 or lb2 lock bits are set. otherwise, the on-chi p debug system would have provided a back-door into a secu red device. the avr studio enables the user to fully contro l execution of programs on an avr device with on-chip debug capability, avr in- circuit emulator, or the built-i n avr instruction set simulator. avr studio ? supports source level execution of assembly programs assembled with atmel cor- poration?s avr assembler and c programs compiled with third party vendors? compilers. avr studio runs under microsoft ? windows ? 95/98/2000/nt/xp. for a full description of the avr studio, please re fer to the avr studio user guide. only high- lights are presented in this document. all necessary execution commands are available in avr studio, both on source level and on disassembly level. the user can execute the program, single step through the code either by tracing into or stepping over functions, step ou t of functions, place the cursor on a statement and execute until the st atement is reached, stop the executio n, and reset the execution target. in addition, the user can have an unlimited number of code break points (using the break instruction) and up to two data memory break points, alternatively combined as a mask (range) break point. 22.7 on-chip debug specific jtag instructions the on-chip debug support is considered being pr ivate jtag instructions, and distributed within atmel and to selected third pa rty vendors only. instruction opcodes are listed for reference. 22.7.1 private0 (0x8) private jtag instruction for accessing on-chip debug system. 22.7.2 private1 (0x9) private jtag instruction for accessing on-chip debug system. 22.7.3 private2 (0xa) private jtag instruction for accessing on-chip debug system. 22.7.4 private3 (0xb) private jtag instruction for accessing on-chip debug system. 299 7679h?can?08/08 at90can32/64/128 22.8 on-chip debug related register in i/o memory 22.8.1 on-chip debug register ? ocdr the ocdr register provides a co mmunication channel from the running pr ogram in the micro- controller to the debugger. the cpu can transfer a byte to the debugger by writing to this location. at the same time, an in ternal flag; i/o debug register dirty ? idrd ? is set to indicate to the debugger that the register has been writ ten. when the cpu reads the ocdr register the 7 lsb will be from the ocdr regi ster, while the msb is the idrd bit. the debugger clears the idrd bit when it has read the information. in some avr devices, this register is shared wi th a standard i/o location. in this case, the ocdr register can only be accessed if the ocden fuse is programmed, and the debugger enables access to the ocdr register. in all other case s, the standard i/o location is accessed. refer to the debugger documentation for furt her information on how to use this register. 22.9 using the jtag programming capabilities programming of avr parts via jtag is performed via the 4-pin jtag port, tck, tms, tdi, and tdo. these are the only pins that need to be controlled/observed to perform jtag program- ming (in addition to power pins). it is not requi red to apply 12v externally. the jtagen fuse must be programmed and the jtd bit in the mc ucr register must be cleared to enable the jtag test access port. the jtag programmi ng capability supports: ? flash programming and verifying. ? eeprom programming and verifying. ? fuse programming and verifying. ? lock bit programming and verifying. the lock bit security is exactly as in parallel programming mode. if the lock bits lb1 or lb2 are programmed, the ocden fuse cannot be programmed unless first doing a chip erase. this is a security feature that ensures no back-door exists for reading out the content of a secured device. the details on programming through the jtag interface and programming specific jtag instructions are given in the section ?jtag programming overview? on page 352 . 22.10 bibliography for more information about general boundary-scan, the following literature can be consulted: ? ieee: ieee std 1149.1-1990. ieee standard test access port and boundary-scan architecture, ieee, 1993. ? colin maunder: the board designers guide to testable logic circuits, addison-wesley, 1992. bit 7 6543210 idrd/ocdr7 ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr0 ocdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 300 7679h?can?08/08 at90can32/64/128 23. boundary-scan ieee 1149.1 (jtag) 23.1 features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the jtag standard ? full scan of all port functions as well as analog circuitry having off-chip connections ? supports the optional idcode instruction ? additional public avr_reset instruction to reset the avr 23.2 system overview the boundary-scan chain has the capability of drivin g and observing the logi c levels on the digi- tal i/o pins, as well as the boundary between digi tal and analog logic for analog circuitry having off-chip connections. at system level, all ics having jtag capabilities ar e connected serially by the tdi/tdo signals to form a long shift register. an external controller sets up the devices to drive values at their output pins, and observe t he input values received from other devices. the controller compares the received data with the ex pected result. in this way, boundary-scan pro- vides a mechanism for testing interconnections and integrity of components on printed circuits boards by using the four tap signals only. the four ieee 1149.1 defined mandatory jtag in structions idcode, bypass, sample/pre- load, and extest, as well as the avr specif ic public jtag instruction avr_reset can be used for testing the prin ted circuit board. initia l scanning of the data register path will show the id-code of the device, since idcode is the default jtag instruction. it may be desirable to have the avr device in reset during test mode. if not reset, inputs to the device may be deter- mined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. en tering reset, the outputs of any po rt pin will instantly enter the high impedance state, making the highz instruction redundant. if needed, the bypass instruction can be issued to make the shortest possible scan chain through the device. the device can be set in the reset state either by pulling the external reset pin low, or issuing the avr_reset instruction with appropriate setti ng of the reset data register. the extest instruction is used for sampling exte rnal pins and loading output pins with data. the data from the output latch will be driven out on the pins as soon as the extest instruction is loaded into the jtag ir-register. therefore, the sample/preload should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the extest instruction for the first time. sample/preload c an also be used for taking a snapshot of the external pins during normal operation of the part. the jtagen fuse must be prog rammed and the jtd bit in th e i/o register mcucr must be cleared to enable the jtag test access port. when using the jtag interface for boundary-scan, using a jtag tck clock frequency higher than the internal chip frequency is possible. the chip clock is not required to run. 23.3 data registers the data registers relevant for boundary-scan operations are: ? bypass register ? device identific ation register ? reset register ? boundary-scan chain 301 7679h?can?08/08 at90can32/64/128 23.3.1 bypass register the bypass register consists of a single shi ft register stage. when the bypass register is selected as path between tdi and tdo, the regist er is reset to 0 when leaving the capture-dr controller state. the bypass register may be us ed to shorten the scan chain on a system when the other devices are to be tested. 23.3.2 device identification register figure 23-1 shows the structure of the de vice identification register. figure 23-1. the format of the device identification register 23.3.2.1 version version is a 4-bit number identifying the revision of the component. the relevant version number is shown in table 23-1 . 23.3.2.2 part number the part number is a 16-bit code identifying the component. the jtag part number for at90can32/64/128 is listed in table 23-2 . 23.3.2.3 manufacturer id the manufacturer id is a 11-bit code identify ing the manufacturer. the jtag manufacturer id for atmel is listed in table 23-3 . msb lsb bit 31 2827 1211 1 0 device id version part number manufacturer id 1 4 bits 16 bits 11 bits 1-bit table 23-1. jtag version numbers version jtag version number (hex) at90can32 revision a 0x0 at90can64 revision a 0x0 at90can128 revision a 0x0 table 23-2. avr jtag part number part number jtag part number (hex) at90can32 0x9581 at90can64 0x9681 at90can128 0x9781 table 23-3. manufacturer id manufacturer jtag manu facturer id (hex) atmel 0x01f 302 7679h?can?08/08 at90can32/64/128 23.3.2.4 device id the full device id is listed in table 23-4 following the at90can32/64/128 version. 23.3.3 reset register the reset register is a test data register used to reset the part. since the avr tri-states port pins when reset, the reset register can also re place the function of the unimplemented optional jtag instruction highz. a high value in the reset register corresponds to pulling the external reset low. the part is reset as long as there is a high value present in the reset register. depending on the fuse set- tings for the clock options, the part will remain reset for a reset time-o ut period (refer to ?system clock? on page 37 ) after releasing the reset register. the output from this data register is not latched, so the reset will take place immediately, as shown in figure 23-2 . figure 23-2. reset register 23.3.4 boundary-scan chain the boundary-scan chain has the capability of driv ing and observing the lo gic levels on the dig- ital i/o pins, as well as the boundary between di gital and analog logic for analog circuitry having off-chip connections. see ?boundary-scan chain? on page 304 for a complete description. 23.4 boundary-scan specifi c jtag instructions the instruction register is 4-bit wide, supportin g up to 16 instructions. listed below are the jtag instructions useful for boundary- scan operation. note that the opt ional highz instruction is not implemented, but all outputs with tri-state capabili ty can be set in high-impedant state by using the avr_reset instruction, since the initia l state for all port pins is tri-state. as a definition in this datasheet, the lsb is shifted in and out first for all shift registers. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. table 23-4. device id version jtag device id (hex) at90can32 revision a 0x0958103f at90can64 revision a 0x0968103f at90can128 revision a 0x0978103f dq from tdi clockdr ? avr_reset to tdo from other internal and external reset sources internal reset 303 7679h?can?08/08 at90can32/64/128 23.4.1 extest (0x0) mandatory jtag instruction for selecting the bo undary-scan chain as data register for testing circuitry external to the avr package. for port-pins, pull-up disable, output control, output data, and input data are all accessible in the scan chain. for analog ci rcuits having off-chip connections, the interface between the analog and the digital logic is in the scan chain. the con- tents of the latched outputs of the boundary-scan chain is driven out as soon as the jtag ir- register is loaded with the extest instruction. the active states are: ? capture-dr : data on the external pins are sampled into the boundary-scan chain. ? shift-dr : the internal scan chain is shifted by the tck input. ? update-dr : data from the scan chain is applied to output pins. 23.4.2 idcode (0x1) optional jtag instruction selecting the 32 bit id -register as data register. the id-register con- sists of a version number, a device number and the manufacturer code chosen by jedec. this is the default instruction after power-up. the active states are: ? capture-dr : data in the idcode register is sampled into the boundary-scan chain. ? shift-dr : the idcode scan chain is shifted by the tck input. 23.4.3 sample_preload (0x2) mandatory jtag instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affect ing the system operation. howe ver, the output latches are not connected to the pins. the boundary-scan chain is selected as data register. the active states are: ? capture-dr : data on the external pins are sampled into the boundary-scan chain. ? shift-dr : the boundary-scan chain is shifted by the tck input. ? update-dr : data from the boundary-scan chain is applied to the output latches. however, the output latches are not connected to the pins. 23.4.4 avr_reset (0xc) the avr specific public jtag instruction for forcing the avr device into the reset mode or releasing the jtag reset source. the tap controller is not reset by this in struction. the one bit reset register is selected as data register. note that the reset will be active as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the active states are: ? shift-dr : the reset register is shifted by the tck input. 23.4.5 bypass (0xf) mandatory jtag instruction selecting the bypass register for data register. the active states are: ? capture-dr : loads a logic ?0? into the bypass register. 304 7679h?can?08/08 at90can32/64/128 ? shift-dr : the bypass register cell between tdi and tdo is shifted. 23.5 boundary-scan related register in i/o memory 23.5.1 mcu control register ? mcucr the mcu control register contains co ntrol bits for general mcu functions. ? bits 7 ? jtd: jtag interface disable when this bit is zero, the jtag interface is ena bled if the jtagen fuse is programmed. if this bit is one, the jtag interface is disabled. in order to avoid unintentional disabling or enabling of the jtag interface, a timed sequence must be followed when changing this bit: the application software must write this bit to the desired value twice within four cycles to change its value. note that this bit must not be altered when using the on-chip debug system. if the jtag interface is left unconnected to ot her jtag circuitry, the jtd bit should be set to one. the reason for this is to avoid static current at the tdo pin in the jtag interface. 23.5.2 mcu status register ? mcusr the mcu status register provides information on which reset source caused an mcu reset. ? bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caused by a logic one in the jtag reset register selected by the jtag instruction avr_reset. this bit is rese t by a power-on reset, or by writing a logic zero to the flag. 23.6 boundary-scan chain the boundary-scan chain has the capability of drivin g and observing the logi c levels on the digi- tal i/o pins, as well as the boundary between digi tal and analog logic for analog circuitry having off-chip connection. 23.6.1 scanning the digital port pins figure 23-3 shows the boundary-scan cell for a bi-directional port pin with pull-up function. the cell consists of a standard boundary-scan cell for the pull-up enable ? puexn ? function, and a bi-directional pin cell that combines the three signals output control ? ocxn, output data ? odxn, and input data ? idxn, into only a two-stag e shift register. the port and pin indexes are not used in the following description the boundary-scan logic is not include d in the figures in the datasheet. figure 23-4 shows a simple digital port pin as described in the section ?i/o-ports? on page 66 . the boundary-scan details from figure 23-3 replaces the dashed box in figure 23-4 . bit 76543210 jtd ? ? pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ? ? ?jtrf wdrf borf extrf porf mcusr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 see bit description 305 7679h?can?08/08 at90can32/64/128 when no alternate port function is present, t he input data ? id ? corresponds to the pinxn reg- ister value (but id has no synchronizer), output data corresponds to the port register, output control corresponds to the data direction ? dd register, and the pull-up enable ? puexn ? cor- responds to logic expression pud ddxn portxn. digital alternate port functions are connected outside the dotted box in figure 23-4 to make the scan chain read the actual pin value. for analog function, there is a direct connection from the external pin to the analog circuit, and a scan ch ain is inserted on the interface between the digi- tal logic and the analog circuitry. figure 23-3. boundary-scan cell for bi-directional port pin with pull-up function. dq dq g 0 1 0 1 dq dq g 0 1 0 1 0 1 0 1 dq dq g 0 1 port pin (pxn) vcc extest to next cell shiftdr output control (oc) pullup enable (pue) output data (od) input data (id) from last cell updatedr clockdr ff2 ld2 ff1 ld1 ld0 ff0 306 7679h?can?08/08 at90can32/64/128 figure 23-4. general port pin schematic diagram 23.6.2 boundary-scan and the two-wire interface the two two-wire interface pins scl and sda ha ve one additional cont rol signal in the scan- chain; two-wire interface enable ? twien. as shown in figure 23-5 , the twien signal enables a tri-state buffer with slew-rate control in para llel with the ordinary digital port pins. a general scan cell as shown in figure 23-9 is attached to the twien signal. notes: 1. a separate scan chain for the 50 ns spike f ilter on the input is not provided. the ordinary scan support for digital port pins suffice for connectivity tests. the only reason for having twien in the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary- scan. 2. make sure the oc and twien signals are not asserted simultaneously, as this will lead to drive contention. clk rpx rrx wpx rdx wdx pud synchronizer wdx: write ddrx wpx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data bus sleep sleep: sleep control pxn i/o i/o see boundary-scan description for details! puexn ocxn odxn idxn puexn: pullup enable for pin pxn ocxn: output control for pin pxn odxn: output data to pin pxn idxn: input data from pin pxn 307 7679h?can?08/08 at90can32/64/128 figure 23-5. additional scan signal for the two-wire interface 23.6.3 scanning the reset pin the reset pin accepts 3v or 5v active low logic for standard reset operation, and 12v active high logic for high voltage parallel programming. an observe-only cell as shown in figure 23-6 is inserted both for the 3v or 5v reset signal - rstt, and the 12v reset signal - rsthv. figure 23-6. observe-only cell for reset pin 23.6.4 scanning the clock pins the avr devices have many clock options selectable by fuses. these are: internal rc oscilla- tor, external clock, (high frequency) crystal oscillator, low-frequenc y crystal oscillator, and ceramic resonator. figure 23-7 shows how each oscillator with external connection is supported in the scan chain. the enable signal is supported with a general bo undary-scan cell, while the oscillator/clock out- put is attached to an observe-only cell. in additi on to the main clock, the timer2 oscillator is scanned in the same way. the output from the internal rc oscillator is not scanned, as this oscillator does not have external connections. pxn puexn odxn idxn twien ocxn slew-rate limited src 0 1 dq from previous cell clockdr shiftdr to next cell from system pin to system logic ff1 308 7679h?can?08/08 at90can32/64/128 figure 23-7. boundary-scan cells for os cillators and clock options table 23-5 summaries the scan registers for the exte rnal clock pin xta l1, oscillators with xtal1/xtal2 connections as well as external timer2 clock pin tosc1 and 32khz timer2 oscillator. notes: 1. do not enable more than one clock source as clock at a time. 2. scanning an oscillator output gi ves unpredictable results as there is a frequency drift between the internal oscillator and the jtag tck clock. if possible, scanning an external clock is preferred. 3. the main clock configuration is programmed by fuses. as a fuse is not changed run-time, the main clock configuration is considered fixed fo r a given application. the user is advised to scan the same clock option as to be used in the final system. the enable signals are sup- ported in the scan chain because the system logi c can disable clock options in sleep modes, thereby disconnecting the oscillator pins from the scan path if not provided. 23.6.5 scanning the analog comparator the relevant comparator signals regarding boundary-scan are shown in figure 23-8 . the boundary-scan cell from figure 23-9 is attached to each of these signals. the signals are described in table 23-6 . the comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. table 23-5. scan signals for the oscillators (1)(2)(3) enable signal scanned clock line clock option scanned clock line when not used extclken extclk (xtal1) e xternal main clock 0 oscon oscck external crystal external ceramic resonator 1 osc32en osc32ck low freq. external crystal 1 toskon tosck 32 khz timer2 oscillator 1 0 1 dq from previous cell clockdr shiftdr to next cell to system logic ff1 0 1 dq dq g 0 1 from previous cell clockdr updatedr shiftdr to next cell extest from digital logic xtal1 / tosc1 xtal2 / tosc2 oscillator enable output 309 7679h?can?08/08 at90can32/64/128 figure 23-8. analog comparator figure 23-9. general boundary-scan cell used for signals for comparator and adc table 23-6. boundary-scan signals for the analog comparator signal name direction as seen from the comparator description recommended input when not in use output values when recommended inputs are used ac_idle input turns off analog comparator when true 1 depends upon c code being executed aco output analog comparator output will become input to c code being executed 0 acme input uses output signal from adc mux when true 0 depends upon c code being executed acbg input bandgap reference enable 0 depends upon c code being executed acbg bandgap reference adc multiplexer output acme ac_idle aco adcen 0 1 dq dq g 0 1 from previous cell clockdr updatedr shiftdr to next cell extest to analog circuitry/ to digital logic from digital logic/ from analog ciruitry 310 7679h?can?08/08 at90can32/64/128 23.6.6 scanning the adc figure 23-10 shows a block diagram of the adc with all relevant control and observe signals. the boundary-scan cell from figure 23-9 is attached to each of these signals. the adc need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. figure 23-10. analog to digital converter the signals are described briefly in table 23-7 . + - aref prech dacout comp muxen_7 adc_7 muxen_6 adc_6 muxen_5 adc_5 muxen_4 adc_4 muxen_3 adc_3 muxen_2 adc_2 muxen_1 adc_1 muxen_0 adc_0 negsel_2 adc_2 negsel_1 adc_1 negsel_0 adc_0 extch + - + - 10x 20x 10-bit dac st aclk ampen 2.56v ref irefen aref vccren dac_9..0 adcen hold prech gnden passen acten comp sctest adcbgen to comparator g20 g10 1.22v ref 311 7679h?can?08/08 at90can32/64/128 table 23-7. boundary-scan signals for the adc (1) signal name direction as seen from the adc description recommended input when not in use output values when recommended inputs are used, and cpu is not using the adc comp output comparator output 0 0 aclk input clock signal to gain stages implemented as switch-cap filters 00 acten input enable path from gain stages to the comparator 00 adcbgen input enable band-gap reference as negative input to comparator 00 adcen input power-on signal to the adc 00 ampen input power-on signal to the gain stages 00 dac_9 input bit 9 of digital value to dac 11 dac_8 input bit 8 of digital value to dac 00 dac_7 input bit 7 of digital value to dac 00 dac_6 input bit 6 of digital value to dac 00 dac_5 input bit 5 of digital value to dac 00 dac_4 input bit 4 of digital value to dac 00 dac_3 input bit 3 of digital value to dac 00 dac_2 input bit 2 of digital value to dac 00 dac_1 input bit 1 of digital value to dac 00 dac_0 input bit 0 of digital value to dac 00 extch input connect adc channels 0 - 3 to by-pass path around gain stages 11 g10 input enable 10x gain 0 0 g20 input enable 20x gain 0 0 312 7679h?can?08/08 at90can32/64/128 gnden input ground the negative input to comparator when true 00 hold input sample & hold signal. sample analog signal when low. hold signal when high. if gain stages are used, this signal must go active when aclk is high. 11 irefen input enables band-gap reference as aref signal to dac 00 muxen_7 input input mux bit 7 0 0 muxen_6 input input mux bit 6 0 0 muxen_5 input input mux bit 5 0 0 muxen_4 input input mux bit 4 0 0 muxen_3 input input mux bit 3 0 0 muxen_2 input input mux bit 2 0 0 muxen_1 input input mux bit 1 0 0 muxen_0 input input mux bit 0 1 1 negsel_2 input input mux for negative input for differential signal, bit 2 00 negsel_1 input input mux for negative input for differential signal, bit 1 00 negsel_0 input input mux for negative input for differential signal, bit 0 00 passen input enable pass-gate of gain stages. 11 prech input precharge output latch of comparator. (active low) 11 table 23-7. boundary-scan signals for the adc (1) (continued) signal name direction as seen from the adc description recommended input when not in use output values when recommended inputs are used, and cpu is not using the adc 313 7679h?can?08/08 at90can32/64/128 note: 1. incorrect setting of the switches in figure 23-10 will make signal contention and may damage the part. there are several input choices to th e s&h circuitry on the negative input of the out- put comparator in figure 23-10 . make sure only one path is selected from either one adc pin, bandgap reference source, or ground. if the adc is not to be used during scan, the recommended input values from table 23-7 should be used. the user is recommended not to use the differential gain stages during scan. switch- cap based gain stages require fast operation an d accurate timing which is difficult to obtain when used in a scan chain. details concerning oper ations of the differentia l gain stage is there- fore not provided. the avr adc is based on the analog circuitry shown in figure 23-10 with a successive approx- imation algorithm implemented in the digital logi c. when used in boundary-scan, the problem is usually to ensure that an applied analog voltag e is measured within some limits. this can easily be done without running a successi ve approximation algorithm: apply the lower limit on the digi- tal dac[9:0] lines, make sure the output from the comparator is low, then apply the upper limit on the digital dac[9:0] lines, and verify the output from the comparator to be high. the adc need not be used for pure connectivity te sting, since all analog inputs are shared with a digital port pin as well. when using the adc, remember the following ? the port pin for the adc channel in use must be configured to be an input with pull-up disabled to avoid signal contention. ? in normal mode, a dummy conversion (consis ting of 10 comparisons) is performed when enabling the adc. the user is advised to wait at least 200ns after enabling the adc before controlling/observing any adc sign al, or perform a du mmy conversion before using the first result. ? the dac values must be stable at the midpoint value 0x200 when having the hold signal low (sample mode). as an example, consider the task of verifying a 1.5v 5% i nput signal at adc channel 3 when the power supply is 5.0v and aref is externally connected to v cc. sctest input switch-cap test enable. output from x10 gain stage send out to port pin having adc_4 00 st input output of gain stages will settle faster if this signal is high first two aclk periods after ampen goes high. 00 vccren input selects vcc as the acc reference voltage. 00 the lower limit is: [ 1024 * 1.5v * 0.95 / 5v ] = 291 = 0x123 the upper limit is: [ 1024 * 1.5v * 1.05 / 5v ] = 323 = 0x143 table 23-7. boundary-scan signals for the adc (1) (continued) signal name direction as seen from the adc description recommended input when not in use output values when recommended inputs are used, and cpu is not using the adc 314 7679h?can?08/08 at90can32/64/128 the recommended values from table 23-7 are used unless other values are given in the algo- rithm in table 23-8 . only the dac and port pin values of the scan chain are shown. the column ?actions? describes what jtag instruction to be used before filling the boundary-scan register with the succeeding columns. the verification should be done on the data scanned out when scanning in the data on the same row in the table. using this algorithm, the timing constraint on the hold signal constrains the tck clock fre- quency. as the algorithm keeps hold high for fi ve steps, the tck clock frequency has to be at least five times the number of scan bits divided by the maximum hold time, t hold,max 23.7 at90can32/64/128 b oundary-scan order table 23-9 shows the scan order between tdi and tdo when the boundary-scan chain is selected as data path. bit 0 is the lsb; the first bit scanned in, and the first bit scanned out. the scan order follows the pin-out order as far as possible. therefore, the bits of port a is scanned in the opposite bit order of the other ports. exceptio ns from the rules are the scan chains for the analog circuits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to. in figure 23-3 , pxn. data corresponds to ff0, pxn. control table 23-8. algorithm for using the adc step actions adcen dac muxen hold prech pa3. data pa3. control pa3. pullup_ enable 1 sample_ preload 1 0x200 0x08 1 1 0 0 0 2 extest 1 0x200 0x08 0 1 0 0 0 3 1 0x200 0x08 1 1 0 0 0 4 1 0x123 0x08 1 1 0 0 0 5 1 0x123 0x08 1 0 0 0 0 6 verify the comp bit scanned out to be 0 1 0x200 0x08 1 1 0 0 0 7 1 0x200 0x08 0 1 0 0 0 8 1 0x200 0x08 1 1 0 0 0 9 1 0x143 0x08 1 1 0 0 0 10 1 0x143 0x08 1 0 0 0 0 11 verify the comp bit scanned out to be 1 1 0x200 0x08 1 1 0 0 0 315 7679h?can?08/08 at90can32/64/128 corresponds to ff1, and pxn. pullup_enable correspo nds to ff2. bit 2, 3, 4, and 5 of port c is not in the scan chain, since these pins consti tute the tap pins when the jtag is enabled. table 23-9. at90can32/64/128 boundary-scan order bit number signal name comment module 200 ac_idle comparator 199 aco 198 acme 197 ainbg 196 comp adc 195 aclk 194 acten 193 private_signal (1) 192 adcbgen 191 adcen 190 ampen 189 dac_9 188 dac_8 187 dac_7 186 dac_6 185 dac_5 184 dac_4 183 dac_3 182 dac_2 181 dac_1 180 dac_0 179 extch 178 g10 177 g20 176 gnden 175 hold 174 irefen 173 muxen_7 172 muxen_6 171 muxen_5 170 muxen_4 169 muxen_3 168 muxen_2 167 muxen_1 166 muxen_0 165 negsel_2 316 7679h?can?08/08 at90can32/64/128 164 negsel_1 adc 163 negsel_0 162 passen 161 prech 160 sctest 159 st 158 vccren 157 pe0.data port e 156 pe0.control 155 pe0.pullup_enable 154 pe1.data 153 pe1.control 152 pe1.pullup_enable 151 pe2.data 150 pe2.control 149 pe2.pullup_enable 148 pe3.data 147 pe3.control 146 pe3.pullup_enable 145 pe4.data 144 pe4.control 143 pe4.pullup_enable 142 pe5.data 141 pe5.control 140 pe5.pullup_enable 139 pe6.data 138 pe6.control 137 pe6.pullup_enable 136 pe7.data 135 pe7.control 134 pe7.pullup_enable 133 pb0.data port b 132 pb0.control 131 pb0.pullup_enable 130 pb1.data 129 pb1.control 128 pb1.pullup_enable 127 pb2.data table 23-9. at90can32/64/128 boundary-scan order (continued) bit number signal name comment module 317 7679h?can?08/08 at90can32/64/128 126 pb2.control port b 125 pb2.pullup_enable 124 pb3.data 123 pb3.control 122 pb3.pullup_enable 121 pb4.data 120 pb4.control 119 pb4.pullup_enable 118 pb5.data 117 pb5.control 116 pb5.pullup_enable 115 pb6.data 114 pb6.control 113 pb6.pullup_enable 112 pb7.data 111 pb7.control 110 pb7.pullup_enable 109 pg3.data port g 108 pg3.control 107 pg3.pullup_enable 106 pg4.data 105 pg4.control 104 pg4.pullup_enable 103 private_signal (1) ? 102 rstt (observe only) reset logic 101 rsthv 100 extclken oscillators 99 oscon 98 osc32en 97 toskon 96 extclk (xtal1) 95 oscck 94 osc32ck 93 tosk 92 pd0.data port d 91 pd0.control 90 pd0.pullup_enable 89 pd1.data table 23-9. at90can32/64/128 boundary-scan order (continued) bit number signal name comment module 318 7679h?can?08/08 at90can32/64/128 88 pd1.control port d 87 pd1.pullup_enable 86 pd2.data 85 pd2.control 84 pd2.pullup_enable 83 pd3.data 82 pd3.control 81 pd3.pullup_enable 80 pd4.data 79 pd4.control 78 pd4.pullup_enable 77 pd5.data 76 pd5.control 75 pd5.pullup_enable 74 pd6.data 73 pd6.control 72 pd6.pullup_enable 71 pd7.data 70 pd7.control 69 pd7.pullup_enable 68 pg0.data port g 67 pg0.control 66 pg0.pullup_enable 65 pg1.data 64 pg1.control 63 pg1.pullup_enable 62 pc0.data port c 61 pc0.control 60 pc0.pullup_enable 59 pc1.data 58 pc1.control 57 pc1.pullup_enable 56 pc2.data 55 pc2.control 54 pc2.pullup_enable 53 pc3.data 52 pc3.control 51 pc3.pullup_enable table 23-9. at90can32/64/128 boundary-scan order (continued) bit number signal name comment module 319 7679h?can?08/08 at90can32/64/128 50 pc4.data port c 49 pc4.control 48 pc4.pullup_enable 47 pc5.data 46 pc5.control 45 pc5.pullup_enable 44 pc6.data 43 pc6.control 42 pc6.pullup_enable 41 pc7.data 40 pc7.control 39 pc7.pullup_enable 38 pg2.data port g 37 pg2.control 36 pg2.pullup_enable 35 pa7.data port a 34 pa7.control 33 pa7.pullup_enable 32 pa6.data 31 pa6.control 30 pa6.pullup_enable 29 pa5.data 28 pa5.control 27 pa5.pullup_enable 26 pa4.data 25 pa4.control 24 pa4.pullup_enable 23 pa3.data 22 pa3.control 21 pa3.pullup_enable 20 pa2.data 19 pa2.control 18 pa2.pullup_enable 17 pa1.data 16 pa1.control 15 pa1.pullup_enable 14 pa0.data 13 pa0.control table 23-9. at90can32/64/128 boundary-scan order (continued) bit number signal name comment module 320 7679h?can?08/08 at90can32/64/128 notes: 1. private_signal should always be scanned-in as zero. 23.8 boundary-scan description language files boundary-scan description language (bsdl) files describe boundary-scan capable devices in a standard format used by automated test-generat ion software. the order and function of bits in the boundary-scan data register are included in this description. a bsdl file for at90can32/64/128 is available. 12 pa0.pullup_enable port a 11 pf3.data port f 10 pf3.control 9 pf3.pullup_enable 8pf2.data 7 pf2.control 6 pf2.pullup_enable 5pf1.data 4 pf1.control 3 pf1.pullup_enable 2pf0.data 1 pf0.control 0 pf0.pullup_enable table 23-9. at90can32/64/128 boundary-scan order (continued) bit number signal name comment module 321 7679h?can?08/08 at90can32/64/128 24. boot loader supp ort ? read-while-wri te self-programming the boot loader support provides a real read- while-write self-programming mechanism for downloading and uploading program code by the m cu itself. this feature a llows flexible applica- tion software updates controlled by the mcu us ing a flash-resident boot loader program. the boot loader program can use any available data interface and associated protocol to read code and write (program) that code into the flash memory, or read the code from the program mem- ory. the program code within the boot loader sect ion has the capability to write into the entire flash, including the boot loader memory. the boot loader can t hus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configurable with fuses and t he boot loader has two separate sets of boot lock bits which can be set indepen dently. this gives the user a uniq ue flexibility to select differ- ent levels of protection. 24.1 features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexible protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modi fy-write support note: 1. a page is a section in the flash consisting of several bytes (see table 25-11 on page 341 ) used during programming. the page organization does not affect normal operation. 24.2 application and boot loader flash sections the flash memory is organized in two main sections, the application section and the boot loader section (see figure 24-2 ). the size of the different se ctions is configured by the bootsz fuses as shown in table 24-6 on page 334 and figure 24-2 . these two sections can have different level of protection since they have different sets of lock bits. 24.2.1 as - application section the application section is the section of the flas h that is used for storing the application code. the protection level for the application section can be selected by the application boot lock bits (blb02 and blb01 bits), see table 24-2 on page 325 . the application section can never store any boot loader code since the spm instruction is disabled when executed from the application section. 24.2.2 bls ? boot loader section while the application section is used for storing the application code, the the boot loader soft- ware must be located in the bls since the spm instruction can initiate a programming when executing from the bls only. the spm instruct ion can access the entir e flash, including the bls itself. the protection level for the boot loader section can be selected by the boot loader lock bits (blb12 and blb11 bits), see table 24-3 on page 325 . 24.3 read-while-write and no r ead-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader soft- ware update is dependent on which address that is being programmed. in addition to the two 322 7679h?can?08/08 at90can32/64/128 sections that are configurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read-whi le-write (rww) secti on and the no read-while- write (nrww) section. the limit between the rww- and nrww sections is given in table 24- 7 on page 334 and figure 24-2 on page 324 . the main difference between the two sections is: ? when erasing or writing a page located insi de the rww section, the nrww section can be read during the operation. ? when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation. note that the user software can never read any code that is located insi de the rww section dur- ing a boot loader software operation. the syntax ?read-while-write sect ion? refers to which section that is being programmed (erased or writ ten), not which section that actually is being read during a boot loader software update. 24.3.1 rww ? read-while-write section if a boot loader software update is programmin g a page inside the rww section, it is possible to read code from the flash, but only code that is located in the nrww section. during an on- going programming, the software must ensure that the rww section never is being read. if the user software is trying to read code that is located inside the rww section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. to avoid this, the interrupts should either be disabled or moved to the boot loader sec- tion. the boot loader section is always loca ted in the nrww section. the rww section busy bit (rwwsb) in the store program memory cont rol and status register (spmcsr) will be read as logical one as long as the rww section is blocked for reading. after a programming is com- pleted, the rwwsb must be cleared by software before reading code located in the rww section. see ?store program memory control and status register ? spmcsr? on page 326. for details on how to clear rwwsb. 24.3.2 nrww ? no read -while-write section the code located in the nrww section can be re ad when the boot loader software is updating a page in the rww section. when the boot l oader code updates the nrww section, the cpu is halted during the entire page erase or page write operation. table 24-1. read-while-write features which section does the z-pointer address during the programming? which section can be read during programming? is the cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no 323 7679h?can?08/08 at90can32/64/128 figure 24-1. read-while-write vs. no read-while-write read-while-write (rww) section no read-while-write (nrww) section z-pointer addresses rww section z-pointer addresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation 324 7679h?can?08/08 at90can32/64/128 figure 24-2. memory sections note: the parameters in the figure above are given in table 24-6 on page 334 . 24.4 boot loader lock bits if no boot loader capability is n eeded, the entire flash is available for application code. the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to sele ct different levels of protection. the user can select: ? to protect the entire flash from a software update by the mcu. ? to protect only the boot loader flash sect ion from a software update by the mcu. ? to protect only the application flash se ction from a software update by the mcu. 0x0000 flashend program memory bootsz = ?11? application flash section boot loader flash section flashend program memory bootsz = ?10? 0x0000 program memory bootsz = ?01? program memory bootsz = ?00? application flash section boot loader flash section 0x0000 flash end application flash section flash end end rww start nrww application flash section boot loader flash section boot loader flash section end rww start nrww end rww start nrww 0x0000 end rww, end application start nrww, start boot loader application flash section application flash section application flash section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section end application start boot loader end application start boot loader end application start boot loader 325 7679h?can?08/08 at90can32/64/128 ? allow software update in the entire flash. see table 24-2 and table 24-3 for further details. th e boot lock bits can be set in software and in serial or parallel programming mode, but they can be cleared by a chip erase command only. the general write lock (lock bit mode 2) does not control the programming of the flash memory by spm instruction. sim ilarly, the general read/write lock (lock bit mode 1) does not control reading nor writing by lpm/spm (lo ad program memory / store program memory) instructions, if it is attempted. note: 1. ?1? means unprogrammed, ?0? means programmed note: 1. ?1? means unprogrammed, ?0? means programmed 24.5 entering the boot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trigger such as a command receiv ed via usart, or spi interface. alternatively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the applica- tion code is loaded, the program can start execut ing the application code. note that the fuses cannot be changed by the mcu itself. this means that once the boot reset fuse is pro- table 24-2. boot lock bit0 protection modes (application section) (1) lock bit mode blb02 blb01 protection 1 1 1 no restrictions for spm or lp m accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot load er section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interr upts are disabled while executing from the application section. table 24-3. boot lock bit1 protection modes (boot loader section) (1) lock bit mode blb12 blb11 protection 111 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to t he boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from the boot loader section. if in terrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 326 7679h?can?08/08 at90can32/64/128 grammed, the reset vector will always point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. note: 1. ?1? means unprogrammed, ?0? means programmed 24.5.1 store program memory control and status register ? spmcsr the store program memory control and status regi ster contains the control bits needed to con- trol the boot loader operations. ? bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, and the i-bi t in the status register is set (one), the spm ready interrupt will be enabled. the spm ready in terrupt will be ex ecuted as long as the spmen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operation to the rww section is initi- ated, the rwwsb will be set (one ) by hardware. when the rwwsb bit is set, the rww section cannot be accessed. the rwwsb bit will be cleared if the rwwsre bit is written to one after a self-programming operation is completed. alter natively the rwwsb bit will automatically be cleared if a page load operation is initiated. ? bit 5 ? res: reserved bit this bit is a reserved bit in the at90can32/64/128 and always read as zero. ? bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the rww section, the rww section is blocked for reading (the rwwsb will be set by ha rdware). to re-enable the rww section, the user software must wait until the programming is complet ed (spmen will be cl eared). then, if the rwwsre bit is written to one at the same time as spmen, the next spm instruction within four clock cycles re-enables the rww secti on. the rww section cannot be re-enabled while the flash is busy with a page erase or a page wr ite (spmen is set). if the rwwsre bit is writ- ten while the flash is being loaded, the flash load operation will abort and the data loaded will be lost. ? bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as spmen, the next spm inst ruction within four clock cycles sets boot lock bits, according to the data in r0. the data in r1 and the address in the z- pointer are ignored. the blbset bit will autom atically be cleared upon completion of the lock bit set, or if no spm instruction is executed within four clock cycles. table 24-4. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 24-6 on page 334 ) bit 7 6 5 4 3 2 1 0 spmie rwwsb ? rwwsre blbset pgwrt pgers spmen spmcsr read/write r/w r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 327 7679h?can?08/08 at90can32/64/128 an lpm instruction within three cycles after blbset and spmen are set in the spmcsr reg- ister, will read either the lock bits or the fuse bits (depending on z0 in the z-pointer) into the destination register. see ?reading the fuse and lock bits from software? on page 330 for details. ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as spmen, the next spm inst ruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon co mpletion of a page write, or if no spm instruction is ex ecuted within four clock cycles. the cpu is halted during the ent ire page write operation if the nrww section is addressed. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spmen, the next spm inst ruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bi t will auto-clear upon comp letion of a page erase, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. ? bit 0 ? spmen: store program memory enable this bit enables the spm instruction for the next fo ur clock cycles. if written to one together with either rwwsre, blbset, pgwrt? or pgers, t he following spm instruction will have a spe- cial meaning, see description abo ve. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit will aut o-clear upon completion of an spm instruction, or if no spm instruction is executed within fo ur clock cycles. during page erase and page write, the spmen bit remains high until the operation is completed. writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. 24.6 addressing the flash during self-programming the z-pointer is used to address the spm commands. the z pointer consists of the z-registers zl and zh in the register file, and rampz in the i/o space. the number of bits actually used is implementation dependent. note that the rampz register is only implemented when the pro- gram space is larger than 64k bytes. since the flash is organized in pages (see table 25-11 on page 341 ), the program counter can be treated as having two different sections. one sect ion, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is shown in figure 24-3 . note that the page erase and page write operations are addressed independently. therefore it is of major importance that the boot loader software addresses the bit 2322212019181716 15 14 13 12 11 10 9 8 rampz ???????rampz0 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7z6z5z4z3z2z1z0 76543210 328 7679h?can?08/08 at90can32/64/128 same page in both the page erase and page writ e operation. once a programming operation is initiated, the address is latched and the z-pointer can be used for other operations. the (e)lpm instruction use the z-pointer to st ore the address. since this instruction addresses the flash byte-by-byte, also bit z0 of the z-pointer is used. figure 24-3. addressing the flash during spm (1) note: 1. the different variables used in figure 24-3 are listed in table 24-8 on page 335 . 24.7 self-programming the flash the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buffer is filled one word at a time using spm and the buffer c an be filled either before the page erase command or between a page erase and a page write operation: alternative 1 : fill the buffer be fore a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2 : fill the buffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write program memory 0 1 23 z - pointer bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word page pcword[pagemsb:0]: 00 01 02 pageend page pcword pcpage pcmsb pagemsb program counter 329 7679h?can?08/08 at90can32/64/128 if only a part of the page needs to be changed, th e rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. w hen using alternative 1, the boot loader provides an effective read-mod ify-write feature which a llows the user software to first read the page, do the necessary changes, and then write back the modified data. if alter- native 2 is used, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase and page write operation is addressing the same page. see ?simple assembly code example for a boot loader? on page 332 for an assembly code example. 24.7.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?x0000011? to spmcsr and execute spm within four clock cycl es after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. ? page erase to the rww section: the nrww section can be read during the page erase. ? page erase to the nrww section: the cpu is halted during the operation. 24.7.2 filling the temporary buffer (page loading) to write an instruction word, set up the addres s in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto-erase after a page write operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. no te that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is wr itten in the middle of an spm page load operation, all data loaded will be lost. 24.7.3 performing a page write to execute page write, set up the address in the z-pointer, write ?x0000101? to spmcsr and execute spm within four clock cycl es after writing spmcsr. the data in r1 and r0 is ignored. the page address must be writte n to pcpage. other bits in th e z-pointer will be ignored during this operation. ? page write to the rww section: the nrww section can be read during the page write. ? page write to the nrww section: the cpu is halted during the operation. 24.7.4 using the spm interrupt if the spm interrupt is en abled, the spm interrupt will genera te a constant interrupt when the spmen bit in spmcsr is cleared. this means th at the interrupt can be used instead of polling the spmcsr register in softwar e. when using the spm interrupt, the interrupt vectors should be moved to the bls section to avoid that an in terrupt is accessing the rww section when it is blocked for reading. how to move the interrupts is described in ?interrupts? on page 60 . 24.7.5 consideration while updating bls special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental writ e to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. if it is not necessary to 330 7679h?can?08/08 at90can32/64/128 change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 24.7.6 prevent reading the rww section during self-programming during self-programming (either page erase or page write), the rww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming operation. the rwwsb in the spmcsr will be set as long as the rww section is busy. during self-programming the inte rrupt vector table should be moved to the bls as described in ?interrupts? on page 60 , or the interrupts must be disabled. before addressing the rww section after the programming is completed, the user software must clear the rwwsb by writing the rwwsre. see ?simple assembly code example for a boot loader? on page 332 for an example. 24.7.7 setting the boot loader lock bits by spm to set the boot loader lock bits, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within four cloc k cycles after writing spmcsr. the only accessible lock bits are the boot lock bits that ma y prevent the application and boot loader section from any soft- ware update by the mcu. see table 24-2 and table 24-3 for how the different settings of the boot loader bits affect the flash access. if bits 5..2 in r0 are cleared (zero), the corresponding boot lock bit will be programmed if an spm instruction is executed within four cycles after blbset and spmen are set in spmcsr. the z-pointer is don?t ca re during this operation, but for fu ture compatibility it is recommended to load the z-pointer with 0x0001 (same as used fo r reading the lock bits). for future compatibility it is also recommended to set bits 7, 6, 1, and 0 in r0 to ?1? when writing the lock bits. when programming the lock bits the entire flash can be read during the operation. 24.7.8 eeprom write prevents writing to spmcsr note that an eeprom write oper ation will block all software progra mming to flash. reading the fuses and lock bits from software will also be prevented during t he eeprom write operation. it is recommended that the user checks the status bit (eewe) in the eecr register and verifies that the bit is cleared before writing to the spmcsr register. 24.7.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bi ts from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and spmen bits in spmcsr. when an lpm instruc- tion is executed within three cpu cycles after the blbset and spmen bits are set in spmcsr, the value of the lock bits will be loaded in the destination register. the blbset and spmen bits will auto-clear upon completion of reading the lo ck bits or if no lpm instruction is executed within three cpu cycles or no spm instruction is executed within four cpu cycles. when blb- set and spmen are cleared, lpm will work as described in the instruction set manual. bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 1 1 bit 76543210 rd (z=0x0001) ? ? blb12 blb11 blb02 blb01 lb2 lb1 331 7679h?can?08/08 at90can32/64/128 the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the blbset and spmen bits in spmcsr. when an lpm instruct ion is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination regist er as shown below. refer to table 25-5 on page 338 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. when an lpm instruc- tion is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the fuse high byte (fhb) will be load ed in the destination re gister as shown below. refer to table 25-4 on page 337 for detailed description and mapping of the fuse high byte. when reading the extended fuse byte, load 0x0002 in the z-pointer. when an lpm instruction is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the extended fuse byte (efb) will be loaded in the desti nation register as shown below. refer to table 25-3 on page 337 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are programmed, will be read as zero. fuse and lock bits that are unprogrammed, will be read as one. 24.7.10 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by tw o situations when the voltage is too low. ? first, a regular write sequence to the flash requires a minimum voltage to operate correctly. ? secondly, the cpu itself can execute instruct ions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. if there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader software updates. 2. keep the avr reset active (low) during peri ods of insufficient po wer supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the po wer supply voltage is sufficient. bit 76543210 rd (z=0x0000) flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd (z=0x0003) fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 76543210 rd (z=0x0002) ? ? ? ? efb3 efb2 efb1 efb0 332 7679h?can?08/08 at90can32/64/128 3. keep the avr core in power-down sleep mode during periods of low v cc . this will pre- vent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from unintentional writes. 24.7.11 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 24-5 shows the typical pro- gramming time for flash accesses from the cpu. 24.7.12 simple assembly code example for a boot loader ;- the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y-pointer ; the first data location in flash is pointed to by the z-pointer ;- error handling is not included ;- the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;- registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcsrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;- it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcsrval, (1< 335 7679h?can?08/08 at90can32/64/128 notes: 1. see ?addressing the flash during self-programming? on page 327 for details about the use of z-pointer during self-programming. 2. z0: should be zero for all spm commands, byte select for the (e)lpm instruction. 3. the z-register is only 16 bits wide. bit 16 is located in rampz register in i/o map. table 24-8. explanation of different variables used in figure 24-3 on page 328 and the mapping to the z-pointer (1) device variable name variable value corresponding z-value description (2) at90can32 pcmsb 13 most significant bit in the program coun ter. (the program counter is 14 bits pc[13:0]) pagemsb 6 most significant bit which is used to address the words within one page (128 words in a page requires 7 bits pc [6:0]). zpcmsb z14 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z7 bit in z-register that is mapped to page msb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[13:7] z14:z7 program counter page address: page select, for page erase and page write. pcword pc[6:0] z7:z1 program counter word address: word select, for filling temporary buffer (must be zero during page write operation). at90can64 pcmsb 14 most significant bit in the program coun ter. (the program counter is 15 bits pc[14:0]) pagemsb 6 most significant bit which is used to address the words within one page (128 words in a page requires 7 bits pc [6:0]). zpcmsb z15 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z7 bit in z-register that is mapped to page msb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[14:7] z15:z7 program counter page address: page select, for page erase and page write. pcword pc[6:0] z7:z1 program counter word address: word select, for filling temporary buffer (must be zero during page write operation). at90can128 pcmsb 15 most significant bit in the program coun ter. (the program counter is 16 bits pc[15:0]) pagemsb 6 most significant bit which is used to address the words within one page (128 words in a page requires 7 bits pc [6:0]). zpcmsb z16 (3) bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z7 bit in z-register that is mapped to page msb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[15:7] z16 (3) :z7 program counter page address: page select, for page erase and page write. pcword pc[6:0] z7:z1 program counter word address: word select, for filling temporary buffer (must be zero during page write operation). 336 7679h?can?08/08 at90can32/64/128 25. memory programming 25.1 program and data memory lock bits the at90can32/64/128 provides six lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 25-2 . the lock bits can only be erased to ?1? with the chip erase command. note: 1. ?1? means unprogrammed, ?0? means programmed. table 25-1. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 1 (unprogrammed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 25-2. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and verification of the flash and eeprom is disabled in parallel and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) blb0 mode blb02 blb01 111 no restrictions for spm (store program memory) or lpm (load program memory) accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the a pplication section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing fr om the application section. 401 lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. blb1 mode blb12 blb11 1 1 1 no restrictions for spm or lpm accessing the boot loader section. 337 7679h?can?08/08 at90can32/64/128 notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed 25.2 fuse bits the at90can32/64/128 has three fuse bytes. table 25-3 , table 25-4 and table 25-5 describe briefly the functionality of all the fuses and how t hey are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. note: 1. see table 7-2 on page 54 for bodlevel fuse decoding. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 lpm executing from the application sect ion is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. table 25-2. lock bit protection modes (1)(2) (continued) memory lock bits protection type table 25-3. extended fuse byte fuse extended byte bit no description default value ?7? 1 ?6? 1 ?5? 1 ?4? 1 bodlevel2 (1) 3 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (1) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (1) 1 brown-out detector trigger level 1 (unprogrammed) ta0sel 0 (reserved for factory tests) 1 (unprogrammed) table 25-4. fuse high byte fuse high byte bit no description default value ocden (4) 7 enable ocd 1 (unprogrammed, ocd disabled) jtagen (5) 6 enable jtag 0 (programmed, jtag enabled) spien (1) 5 enable serial program and data downloading 0 (programmed, spi prog. enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved) 338 7679h?can?08/08 at90can32/64/128 notes: 1. the spien fuse is not accessible in serial programming mode. 2. the default value of bootsz1..0 results in maximum boot size. see table 24-6 on page 334 for details. 3. see ?watchdog timer control register ? wdtcr? on page 58 for details. 4. never ship a product with the ocden fuse programmed regardless of the setting of lock bits and jtagen fuse. a programmed ocden fuse enables some parts of the clock system to be running in all sleep modes. this may increase the power consumption. 5. if the jtag interface is left unconnected, the jtag en fuse should if possible be disabled. this to avoid static current at the tdo pin in the jtag interface. 6. the boot sizes of all the avr ca n microcontrollers are identical. 7. due to the flash size, the boot reset address differs from one avr can microcontroller to another. notes: 1. the default value of sut1..0 results in maximum start-up time for the default clock source. see table 5-8 on page 42 for details. 2. the default settin g of cksel3..0 results in inter nal rc oscillator @ 8 mhz. see table 5-1 on page 38 for details. 3. the ckout fuse allow the system cloc k to be output on port pc7. see ?clock output buffer? on page 43 for details. 4. see ?system clock prescaler? on page 44 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. 25.2.1 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuse s are also latched on power-up in normal mode. bootsz1 2 select boot size (6) (see table 24-6 for details) 0 (programmed) (2) bootsz0 1 select boot size (6) (see table 24-6 for details) 0 (programmed) (2) bootrst 0 select reset vector (7) (see table 24-6 for details) 1 (unprogrammed) table 25-5. fuse low byte fuse low byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) table 25-4. fuse high byte (continued) fuse high byte bit no description default value 339 7679h?can?08/08 at90can32/64/128 25.3 signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. 25.4 calibration byte the at90can32/64/128 has a byte calibration valu e for the internal rc oscillator. this byte resides in the high byte of address 0x000 in th e signature address space. during reset, this byte is automatically written into the osccal regist er to ensure correct frequency of the calibrated rc oscillator. 25.5 parallel progr amming overview this section describes how to parallel progr am and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the at90can32/64/128. pulses are assumed to be at least 250 ns unless otherwise noted. 25.5.1 signal names in this section, some pins of the at90can32/ 64/128 are referenced by signal names describing their functionality during pa rallel programming, see figure 25-1 and table 25-7 . pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a positive pulse. the bit coding is shown in table 25-9 . when pulsing wr or oe , the command loaded determines the action executed. the different commands are shown in table 25-10 . table 25-6. signature bytes device address value signature byte description at90can32 0 0x1e indicates manufactured by atmel 1 0x95 indicates 32 kb flash memory 2 0x81 indicates at90can32 device when address 1 contains 0x95 at90can64 0 0x1e indicates manufactured by atmel 1 0x96 indicates 64 kb flash memory 2 0x81 indicates at90can64 device when address 1 contains 0x96 at90can128 0 0x1e indicates manufactured by atmel 1 0x97 indicates 128 kb flash memory 2 0x81 indicates at90can128 device when address 1 contains 0x97 340 7679h?can?08/08 at90can32/64/128 figure 25-1. parallel programming 25.5.2 pin mapping 25.5.3 commands vcc +2.7 - +5.5v gnd xtal1 pd1 pd2 pd3 pd4 pd5 pd6 pb7 - pb0 data reset pd7 +12 v bs1 xa0 xa1 oe rdy/bsy pagel pa0 wr bs2 avcc +2.7 - +5.5v table 25-7. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command. oe pd2 i output enable (active low). wr pd3 i write pulse (active low). bs1 pd4 i byte select 1 (?0? selects low byte, ?1? selects high byte). xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pagel pd7 i program memory and eeprom data page load. bs2 pa0 i byte select 2 (?0? selects low byte, ?1? selects 2?nd high byte). data pb7-0 i/o bi-directional data bus (output when oe is low). table 25-8. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 341 7679h?can?08/08 at90can32/64/128 25.5.4 parameters table 25-9. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 25-10. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom table 25-11. no. of words in a page and no. of pages in the flash device flash size page size pc word no. of pages pcpage pcmsb at90can32 16k words 128 words pc[6:0] 128 pc[13:7] 13 at90can64 32k words 128 words pc[6:0] 256 pc[14:7] 14 at90can128 64k words 128 words pc[6:0] 512 pc[15:7] 15 table 25-12. no. of words in a page and no. of pages in the eeprom device eeprom size page size pc word no. of pages pcpage eeamsb at90can32 1k bytes 8 bytes eea[2:0] 128 eea[9:3] 9 at90can64 2k bytes 8 bytes eea[2:0] 256 eea[10:3] 10 at90can128 4k bytes 8 bytes eea[2:0] 512 eea[11:3] 11 342 7679h?can?08/08 at90can32/64/128 25.6 parallel programming 25.6.1 enter programming mode the following algorithm puts the device in parallel programming mode: 1. apply power between v cc and gnd. 2. set reset to ?0? and toggle xtal1 at least six times. 3. set the prog_enable pins listed in table 25-8 on page 340 to ?0000? and wait at least 100 ns. 4. apply 11.5 - 12.5v to reset . any activity on prog_enable pins within 100 ns after +12v has been applied to reset , will cause the device to fail entering programming mode. 5. wait at least 50 s before sending a new command. 25.6.2 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) a nd flash after a chip erase. ? address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading. 25.6.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be perfor med before the flas h and/or eeprom are reprogrammed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive puls e. this loads the command. 5. give wr a negative pulse. this st arts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. note: 1. the eeprom memory is preserved during chip erase if the eesave fuse is programmed. 25.6.4 programming the flash the flash is organized in pages, see table 25-11 on page 341 . when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be pro- grammed simultaneously. the following procedure describes how to program the entire flash memory: a : load command ?write flash? 343 7679h?can?08/08 at90can32/64/128 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive puls e. this loads the command. b : load address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. c : load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d : load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e : latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes. (see figure 25-3 for signal waveforms) f : repeat b through e until the entire buffer is fill ed or until all data within the page is loaded. while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the fl ash. this is illustrated in figure 25-2 on page 344 . note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. g : load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h : program page 1. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 25-3 for signal waveforms). i : repeat b through h until the entire flash is programmed or until all data has been programmed. j : end page programming 344 7679h?can?08/08 at90can32/64/128 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write signals are reset. figure 25-2. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 25-11 on page 341 . figure 25-3. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters refer to the programming description above. program memory word address within a page page address within the flash instruction word page pcword[pagemsb:0]: 00 01 02 pageend page pcword pcpage pcmsb pagemsb program counter 0x10 addr. low addr. high data low data high addr. low data low data high rdy/bsy wr oe reset +12v pagel bs2 data xa1 xa0 bs1 xtal1 xx xx xx abcdeb cdegh f 345 7679h?can?08/08 at90can32/64/128 25.6.5 programming the eeprom the eeprom is organized in pages, see table 25-12 on page 341 . when programming the eeprom, the program data is latche d into a page buffer. this al lows one page of data to be programmed simultaneously. th e programming algorithm for th e eeprom data memory is as follows (refer to ?programming the flash? on page 342 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k : repeat 3 through 5 until t he entire buffer is filled. l : program eeprom page 1. set bs1 to ?0?. 2. give wr a negative pulse. this starts pr ogramming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 25-4 for signal waveforms). figure 25-4. programming the eeprom waveforms 25.6.6 reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 342 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs1 to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. 0x11 addr. high addr. low data addr. low data xx xx agbceb c el k rdy/bsy wr oe reset +12v pagel bs2 data xa1 xa0 bs1 xtal1 346 7679h?can?08/08 at90can32/64/128 25.6.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 342 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0 ?. the eeprom data byte can now be read at data. 5. set oe to ?1?. 25.6.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 342 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. 25.6.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 342 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. 25.6.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?programming the flash? on page 342 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?0? and bs2 to ?1?. this selects extended data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs2 to ?0?. this selects low data byte. 347 7679h?can?08/08 at90can32/64/128 figure 25-5. programming the fuses waveforms 25.6.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 342 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. 25.6.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 342 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. 0x40 data xx ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte xtal1 bs2 reset +12v rdy/bsy wr oe pagel data xa1 xa0 bs1 348 7679h?can?08/08 at90can32/64/128 figure 25-6. mapping between bs1, bs2 and the fuse and lock bits during read 25.6.13 reading the signature bytes the algorithm for reading the signatur e bytes is as follows (refer to ?programming the flash? on page 342 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs1 to ?0?. the selected signature byte can now be read at data . 4. set oe to ?1?. 25.6.14 reading the calibration byte the algorithm for reading the calibrati on byte is as follows (refer to ?programming the flash? on page 342 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. 25.7 spi serial programming overview this section describes how to serial progra m and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the at90can32/64/128. 25.7.1 signal names both the flash and eeprom memo ry arrays can be programmed us ing the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (out- put). after reset is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. note, in table 25-13 on page 349 , the pin mapping for spi programming is listed. not all pa rts use the spi pins dedicated for the internal spi interface. note that throughout the description about serial downloading, mosi and miso are used to describe the serial data in and se rial data out respectively. for at90can32/64/128 these pins are mapped to pdi (pe0) and pdo (pe1). bs2 data 0 1 bs2 extended fuse byte fuse low byte 0 1 fuse high byte lock bits bs1 0 1 349 7679h?can?08/08 at90can32/64/128 figure 25-7. serial programming and verify (1) notes: 1. if the device is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be present. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck 12 mhz high: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck 12 mhz 25.7.2 pin mapping 25.7.3 parameters the flash parameters are given in table 25-11 on page 341 and the eeprom parameters in table 25-12 on page 341 . 25.8 spi serial programming when writing serial data to t he at90can32/64/128, data is clocked on the rising edge of sck. when reading data from the at 90can32/64/128, data is clocke d on the falling edge of sck. to program and verify the at90can32/64/128 in the serial programming mode, the following sequence is recommended (see four byte instruction formats in table 25-15 ): vcc +2.7 - +5.5v gnd xtal1 pb1 reset pdo pe1 pe0 pdi sck avcc +2.7 - +5.5v table 25-13. pin mapping serial programming symbol pins i/o description mosi (pdi) pe0 i serial data in miso (pdo) pe1 o serial data out sck pb1 i serial clock 350 7679h?can?08/08 at90can32/64/128 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some sys- tems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial programming by sending the programming enable serial instru ction to pin mosi. 3. the serial programming instructions will not work if the communication is out of syn- chronization. when in sync. the second byte (0x53), will ec ho back when issuing the third byte of the programming enable instructio n. whether the echo is correct or not, all four bytes of the instruction must be tran smitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the page size is found in table 25-11 on page 341 . the memory page is loaded one byte at a time by supplying the 7 lsb of the address and data together with the load pr ogram memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for given address. the program memory page is stored by loading the write program memory page instruction with the 9 m sb of the address. if polling is not used, the user must wait at least t wd_flash before issuing the next page. (see table 25-14 ). note: if other commands than polling (read) ar e applied before any write operation (flash, eeprom, lock bits, fuses) is completed, may re sult in incorrect prog ramming. a delay of 1 s is sufficient. 5. the eeprom array is programmed one byte at a time by supplying the address and data together with t he appropriate write in struction. an eeprom memory location is first automatically erased before new data is wr itten. if polling is no t used, the user must wait at least t wd_eeprom before issuing the next byte. (see table 25-14 .) in a chip erased device, no 0xffs in the data file(s) need to be programmed. 6. any memory location can be verified by us ing the read instruct ion which returns the content at the selected addre ss at serial output miso. 7. at the end of the pr ogramming se ssion, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. turn vcc power off. 25.8.1 data polling flash when a page is being programmed into the flash, reading an address location within the page being programmed will give the value 0xff. at th e time the device is ready for a new page, the programmed value will read correctly. this is used to determine w hen the next page can be writ- ten. note that the entire page is written si multaneously and any address within the page can be used for polling. data po lling of the flash will not work for the value 0xff, so when programming this value, the user will have to wait for at least t wd_flash before programming the next page. as a chip-erased device contains 0xff in all locati ons, programming of addresses that are meant to contain 0xff, can be skipped. see table 25-14 for t wd_flash value. 25.8.2 data polling eeprom when a new byte has been written and is being programmed into eeprom, reading the address location being programmed will give the value 0xff. at the time the device is ready for a new byte, the programmed value will read corr ectly. this is used to determine when the next byte can be written. this will not work for the value 0xff, but th e user should have the following in mind: as a chip-erased device contains 0xff in all locations, programming of addresses that 351 7679h?can?08/08 at90can32/64/128 are meant to contain 0xff, can be skipped. this does not apply if the eeprom is re-pro- grammed without chip eras ing the device. in this case, data po lling cannot be used for the value 0xff, and the user will have to wait at least t wd_eeprom before programming the next byte. see table 25-14 for t wd_eeprom value. figure 25-8. serial programming waveforms table 25-14. minimum wait delay before writing the next flash or eeprom location symbol minimum wait delay t wd_fuse 4.5 ms t wd_flash 4.5 ms t wd_eeprom 9.0 ms t wd_erase 9.0 ms msb lsb lsb serial clock input (sck) serial data input (mosi-pdi) (miso-pdo) sample serial data output msb table 25-15. serial programming instruction set set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction instruction format (1) operation (1) byte 1 byte 2 (2) byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming after reset goes low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase eeprom and flash. read program memory 0010 h 000 aaaa aaaa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a : b . load program memory page 0100 h 000 000x xxxx x bbb bbbb iiii iiii write h (high or low) data i to program memory page at word address b . data low byte must be loaded before data high byte is applied within the same address. write program memory page 0100 1100 aaaa aaaa b xxx xxxx xxxx xxxx write program memory page at address a : b . read eeprom memory 1010 0000 000x aaaa bbbb bbbb oooo oooo read data o from eeprom memory at address a : b . write eeprom memory 1100 0000 000x aaaa bbbb bbbb iiii iiii write data i to eeprom memory at address a : b . 352 7679h?can?08/08 at90can32/64/128 notes: 1. all bytes are represented by binary digits (0b...). 2. address bits exceeding pcmsb and eeamsb (see table 25-11 on page 341 and table 25-12 on page 341 ) are don?t care. 25.9 jtag programming overview programming through the jtag interface requires control of the four jtag specific pins: tck, tms, tdi, and tdo. control of the re set and clock pins is not required. to be able to use the jtag interface, the jtag en fuse must be programmed. the device is default shipped with the fuse pr ogrammed. in addition, the jtd bit in mcucr must be cleared. alternatively, if the jtd bit is set, the external reset can be fo rced low. then, the jtd bit will be cleared after two chip clocks, and the jtag pins are available for programming. this provides a means of using the jtag pins as normal port pi ns in running mode while still allowing in-sys- tem programming via the jtag interface. note th at this technique can not be used when using load eeprom memory page (page access) 1100 0001 0000 0000 0000 0 bbb iiii iiii load data i to eeprom memory page buffer. after data is loaded, program eeprom page. write eeprom memory page (page access) 1100 0010 000x aaaa bbbb b000 xxxx xxxx write eeprom page at address a : b . read lockbits 0101 1000 0000 0000 xxxx xxxx xx oo oooo read lock bits. ?0?= programmed , ?1?= unprogrammed . see table 25-1 on page 336 for details. write lock bits 1010 1100 111x xxxx xxxx xxxx 11 ii iiii write lock bits. set bits = ?0? to program lock bits. see table 25-1 on page 336 for details. read signature byte 0011 0000 000x xxxx xxxx xx bb oooo oooo read signature byte o at address b . write fuse low bits 1010 1100 1010 0000 xxxx xxxx iiii iiii set bits = ?0? to prog ram, ?1? to unprogram. see table 25-5 on page 338 for details. write fuse high bits 1010 1100 1010 1000 xxxx xxxx iiii iiii set bits = ?0? to prog ram, ?1? to unprogram. see table 25-4 on page 337 for details. write extended fuse bits 1010 1100 1010 0100 xxxx xxxx xxxx iiii set bits = ?0? to prog ram, ?1? to unprogram. see table 25-3 on page 337 for details. read fuse low bits 0101 0000 0000 0000 xxxx xxxx oooo oooo read fuse bits. ?0?= programmed , ?1?= unprogrammed . see table 25-5 on page 338 for details. read fuse high bits 0101 1000 0000 1000 xxxx xxxx oooo oooo read fuse high bits. ?0?=programmed, ?1?=unprogrammed. see table 25-4 on page 337 for details. read extended fuse bits 0101 0000 0000 1000 xxxx xxxx oooo oooo read extended fuse bits. ?0?=programmed, ?1?=unprogrammed. see table 25-3 on page 337 for details. read calibration byte 0011 1000 000x xxxx 0000 0000 oooo oooo read calibration byte poll rdy/bsy 1111 0000 0000 0000 xxxx xxxx xxxx xxx o if o = ?1?, a programming operation is still busy. wait until this bit returns to ?0? before applying another command. table 25-15. serial programming instruction set (continued) set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction instruction format (1) operation (1) byte 1 byte 2 (2) byte 3 byte4 353 7679h?can?08/08 at90can32/64/128 the jtag pins for boundary-scan or on-chip debug. in these cases the jtag pins must be ded- icated for this purpose. during programming the clock frequency of the tc k input must be less than the maximum fre- quency of the chip. the system clock prescaler can not be used to divide the tck clock input into a sufficientl y low frequency. as a definition in this datasheet, the lsb is shifted in and out first of all shift registers. 25.9.1 programming specific jtag instructions the instruction register is 4- bit wide, supporting up to 16 instru ctions. the jtag instructions useful for programming are listed below. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. the run-test/idle state of the tap controller is used to generate internal clocks. it can also be used as an idle state between jtag sequences . the state machine sequence for changing the instruction word is shown in figure 25-9 . figure 25-9. state machine sequence for changing the instruction word test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 354 7679h?can?08/08 at90can32/64/128 25.9.1.1 avr_reset (0xc) the avr specific public jtag in struction for setting the avr devi ce in the reset mode or taking the device out from the reset mode. the tap cont roller is not reset by th is instruction. the one bit reset register is selected as data register. note that the reset will be active as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the active states are: ? shift-dr: the reset register is shifted by the tck input. 25.9.1.2 prog_enable (0x4) the avr specific public jtag instruction for enabling programming via the jtag port. the 16- bit programming enable register is selected as data register. the active states are the following: ? shift-dr: the programming enable signature is shifted into the data register. ? update-dr: the programming enable signature is compared to the correct value, and programming mode is entered if the signature is valid. 25.9.1.3 prog_commands (0x5) the avr specific public jtag instruction for entering programming commands via the jtag port. the 15-bit programming command register is selected as data regi ster. the active states are the following: ? capture-dr: the result of the previous command is loaded into the data register. ? shift-dr: the data register is shifted by the tc k input, shifting out the result of the previous command and shifting in the new command. ? update-dr: the programming command is applied to the flash inputs ? run-test/idle: one clock cycle is generated, executing the applied command (not always required, see table 25-16 below). 25.9.1.4 prog_pageload (0x6) the avr specific public jtag in struction to directly load the fl ash data page via the jtag port. an 8-bit flash data byte register is selected as the data register. this is physically the 8 lsbs of the programming command register. the active states are the following: ? shift-dr: the flash data byte register is shifted by the tck input. ? update-dr: the content of the flash data byte register is copied into a temporary register. a write sequence is initiated that within 11 tck cycles loads the content of the temporary register into the flash page buffer. the avr automatically alternates between writing the low and the high byte for each new update-dr stat e, starting with the low byte for the first update-dr encountered after entering th e prog_pageload command. the program counter is pre-incremented before writing the low byte, except for the first written byte. this ensures that the first data is written to the address set up by prog_commands, and loading the last location in the page buffer does not make the program counter increment into the next page. 25.9.1.5 prog_pageread (0x7) the avr specific public jtag instruction to dire ctly capture the flash c ontent via the jtag port. an 8-bit flash data byte register is selected as the data register. this is physically the 8 lsbs of the programming command register. the active states are the following: 355 7679h?can?08/08 at90can32/64/128 ? capture-dr: the content of the selected flash byte is captured into the flash data byte register. the avr automatically alternates between reading the low and the high byte for each new capture-dr state, st arting with the low byte for the first capture-dr encountered after entering the prog_pageread command. the program counter is post-incremented after reading each high byte, including the first read byte. this ensures that the first data is captured from the first address set up by prog_commands, and reading the last location in the page makes the program counter increment into the next page. ? shift-dr: the flash data byte register is shifted by the tck input. 25.9.2 data registers the data registers are selected by the jtag instruction registers described in section ?program- ming specific jtag instructions? on page 353 . the data registers relevant for programming operations are: ? reset register ? programming enable register ? programming command register ? flash data byte register 25.9.2.1 reset register the reset register is a test data register used to reset the part during programming. it is required to reset the part before entering programming mode. a high value in the reset register corresponds to pulling the external reset low. the part is reset as long as there is a high val ue present in the reset register. depending on the fuse settings for the clock options, the part will remain reset for a re set time-out period (refer to ?clock sources? on page 38 ) after releasing the reset register. the output from this data register is not latched, so the reset will take place immediately, as shown in figure 23-2 on page 302 . 25.9.2.2 programming enable register the programming enable register is a 16-bit register. the content s of this register is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. when the con- tents of the register is equal to the program ming enable signature, programming via the jtag port is enabled. the register is reset to 0 on power-on reset, and should always be reset when leaving programming mode. figure 25-10. programming enable register tdi tdo d a t a = dq clockdr & prog_enable programming enable 0xa370 356 7679h?can?08/08 at90can32/64/128 25.9.2.3 programming command register the programming command register is a 15-bit regist er. this register is us ed to serially shift in programming commands, and to serially shift out th e result of the previous command, if any. the jtag programming instruction set is shown in table 25-16 . the state sequence when shifting in the programming commands is illustrated in figure 25-12 . figure 25-11. programming command register tdi tdo s t r o b e s a d d r e s s / d a t a flash eeprom fuses lock bits table 25-16. jtag programming instruction set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence (1)(2) tdo sequence (1)(2) notes 1a. chip erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. poll for chip erase complete 0110011_10000000 xxxxx o x_xxxxxxxx (4) 2a. enter flash write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (11) 2c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 2d. load data low byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 2e. load data high byte 0010111_ iiiiiiii xxxxxxx_xxxxxxxx 2f. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 357 7679h?can?08/08 at90can32/64/128 2g. write flash page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 2h. poll for page write complete 0110111_00000000 xxxxx o x_xxxxxxxx (4) 3a. enter flash read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (11) 3c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 3d. read data low and high byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo low byte high byte 4a. enter eeprom write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (11) 4c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 4d. load data byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 4e. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 4f. write eeprom page 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 4g. poll for page write complete 0110011_00000000 xxxxx o x_xxxxxxxx (4) 5a. enter eeprom read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (11) 5c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 5d. read data byte 0110011_ bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 6a. enter fuse write 0100011_01000000 xxxxxxx_xxxxxxxx 6b. load data low byte (8) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (5) 6c. write fuse extended byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 6d. poll for fuse write complete 0110111_00000000 xxxxx o x_xxxxxxxx (4) 6e. load data low byte (9) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (5) table 25-16. jtag programming instruction (continued) set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence (1)(2) tdo sequence (1)(2) notes 358 7679h?can?08/08 at90can32/64/128 6f. write fuse high byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 6g. poll for fuse write complete 0110111_00000000 xxxxx o x_xxxxxxxx (4) 6h. load data low byte (9) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (5) 6i. write fuse low byte 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 6j. poll for fuse write complete 0110011_00000000 xxxxx o x_xxxxxxxx (4) 7a. enter lock bit write 0100011_00100000 xxxxxxx_xxxxxxxx 7b. load data byte (11) 0010011_11 iiiiii xxxxxxx_xxxxxxxx (6) 7c. write lock bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 7d. poll for lock bit write complete 0110011_00000000 xxxxx o x_xxxxxxxx (4) 8a. enter fuse/lock bit read 0100011_00000100 xxxxxxx_xxxxxxxx 8b. read extended fuse byte (8) 0111010_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8c. read fuse high byte (9) 0111110_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8d. read fuse low byte (10) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8e. read lock bits (11) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xx oooooo (7) 8f. read fuses and lock bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo (7) fuse ext. byte fuse high byte fuse low byte lock bits 9a. enter signature byte read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 9c. read signature byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 10a. enter calibration byte read 0100011_00001000 xxxxxxx_xxxxxxxx table 25-16. jtag programming instruction (continued) set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence (1)(2) tdo sequence (1)(2) notes 359 7679h?can?08/08 at90can32/64/128 notes: 1. address bits e xceeding pcmsb and eeamsb ( table 25-11 and table 25-12 ) are don?t care. 2. all tdi and tdo sequences are repr esented by binary digits (0b...). 3. this command sequence is not required if the seven msb are correctly set by the previous command sequence (which is normally the case). 4. repeat until o = ?1?. 5. set bits to ?0? to program the corresponding fuse, ?1? to unprogram the fuse. 6. set bits to ?0? to program the corresponding lock bit, ?1? to leave the lock bit unchanged. 7. ?0? = programmed, ?1? = unprogrammed. 8. the bit mapping for fuses extended byte is listed in table 25-3 on page 337 . 9. the bit mapping for fuses high byte is listed in table 25-4 on page 337 . 10. the bit mapping for fuses low byte is listed in table 25-5 on page 338 . 11. the bit mapping for lock bits byte is listed in table 25-1 on page 336 . 10b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 10c. read calibration byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 11a. load no operation command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx table 25-16. jtag programming instruction (continued) set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence (1)(2) tdo sequence (1)(2) notes 360 7679h?can?08/08 at90can32/64/128 figure 25-12. state machine sequence for changing/reading the data word 25.9.2.4 flash data byte register the flash data byte register provides an ef ficient way to load t he entire flash page buffer before executing page write, or to read out/ver ify the content of the flash. a state machine sets up the control signals to the flash and senses the strobe signals from the flash, thus only the data words need to be shifted in/out. the flash data byte register actually consists of the 8-bit scan chain and a 8-bit temporary reg- ister. during page load, the update-dr state copies the content of the scan chain over to the temporary register and initiates a write sequence that within 11 tck cycles loads the content of the temporary register into the flash page bu ffer. the avr automatically alternates between writing the low and the high byte for each new up date-dr state, starting with the low byte for the first update-dr encountered after entering t he prog_pageload command. the program counter is pre-incremented before writing the low byte, except for the first written byte. this ensures that the first data is written to th e address set up by prog_commands, and loading the last location in the page buffer does not ma ke the program counter increment into the next page. during page read, the content of the selected flash byte is captured into the flash data byte register during the capture-dr state. the avr automatically alternates between reading the low and the high byte for each new capture-dr stat e, starting with the low byte for the first cap- test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 361 7679h?can?08/08 at90can32/64/128 ture-dr encountered after entering the pr og_pageread command. the program counter is post-incremented after reading each high byte, incl uding the first read byte. this ensures that the first data is captured from the first ad dress set up by prog_commands, and reading the last location in the page makes the progra m counter increment into the next page. figure 25-13. flash data byte register the state machine controlling the flash data by te register is clocked by tck. during normal operation in which eight bits are shifted for eac h flash byte, the clock cycles needed to navigate through the tap controller automatically feeds th e state machine for the flash data byte regis- ter with sufficient number of clock pulses to complete its operation transparently for the user. however, if too few bits are shifted between each update-dr state during page load, the tap controller should stay in the run-test/idle state for some tck cycles to en sure that there are at least 11 tck cycles between each update-dr state. 25.9.3 programming algorithm all references below of type ?1a?, ?1b?, and so on, refer to table 25-16 on page 356 . 25.9.3.1 entering programming mode 1. enter jtag instructio n avr_reset and shift 1 in the reset register. 2. enter instruction prog_enable and shift 0b1010_0011_0111_0000 in the program- ming enable register. 25.9.3.2 leaving programming mode 1. enter jtag instruction prog_commands. 2. disable all programming instructions by using no operation instruction 11a. 3. enter instruction prog_enable and shift 0b0000_0000_0000_0000 in the program- ming enable register. 4. enter jtag instructio n avr_reset and shift 0 in the reset register. tdi tdo d a t a flash eeprom fuses lock bits strobes address state machine 362 7679h?can?08/08 at90can32/64/128 25.9.3.3 performing chip erase 1. enter jtag instruction prog_commands. 2. start chip erase using programming instruction 1a. 3. poll for chip erase comple te using programming instruction 1b, or wait for t wlrh_ce (refer to table 26-15 on page 382 ). 25.9.3.4 programming the flash 1. enter jtag instruction prog_commands. 2. enable flash write using programming instruction 2a. 3. load address high byte using programming instruction 2b. 4. load address low byte using programming instruction 2c. 5. load data using programming instructions 2d, 2e and 2f. 6. repeat steps 4 and 5 for all instruction words in the page. 7. write the page using programming instruction 2g. 8. poll for flash write complete using prog ramming instruction 2h, or wait for t wlrh (refer to ). 9. repeat steps 3 to 7 until all data have been programmed. a more efficient data transfer can be achieved using the prog_pageload instruction: 1. enter jtag instruction prog_commands. 2. enable flash write using programming instruction 2a. 3. load the page address using programming instructions 2b and 2c. pcword (refer to table 25-11 on page 341 ) is used to address within one page and must be written as 0. 4. enter jtag instruction prog_pageload. 5. load the entire page by shifting in all instruction words in the page byte-by-byte, start- ing with the lsb of the first instruction in the page and ending with the msb of the last instruction in the page. use update-dr to c opy the contents of the flash data byte register into the flash page location an d to auto-increment the program counter before each new word. 6. enter jtag instruction prog_commands. 7. write the page using programming instruction 2g. 8. poll for flash write complete using prog ramming instruction 2h, or wait for t wlrh (refer to table 26-15 on page 382 ). 9. repeat steps 3 to 8 until all data have been programmed. 25.9.3.5 reading the flash 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3a. 3. load address using programming instructions 3b and 3c. 4. read data using programming instruction 3d. 5. repeat steps 3 and 4 until all data have been read. a more efficient data transfer can be achieved usi ng the prog_pageread instruction: 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3a. 3. load the page address using programming instructions 3b and 3c. pcword (refer to table 25-11 on page 341 ) is used to address within one page and must be written as 0. 363 7679h?can?08/08 at90can32/64/128 4. enter jtag instruction prog_pageread. 5. read the entire page (or flash) by shifting out all instruction words in the page (or flash), starting with the lsb of the first inst ruction in the page (flash) and ending with the msb of the last instructio n in the page (flash). the c apture-dr state both captures the data from the flash, and also auto-inc rements the program counter after each word is read. note that capture-dr comes before the shift-dr state. hence, the first byte which is shifted out contains valid data. 6. enter jtag instruction prog_commands. 7. repeat steps 3 to 6 until all data have been read. 25.9.3.6 programming the eeprom 1. enter jtag instruction prog_commands. 2. enable eeprom write usin g programming instruction 4a. 3. load address high byte using programming instruction 4b. 4. load address low byte using programming instruction 4c. 5. load data using programming instructions 4d and 4e. 6. repeat steps 4 and 5 for all data bytes in the page. 7. write the data using programming instruction 4f. 8. poll for eeprom write comple te using programming instru ction 4g, or wait for t wlrh (refer to table 26-15 on page 382 ). 9. repeat steps 3 to 8 until all data have been programmed. note that the prog_pageload instruction can not be used when programmi ng the eeprom. 25.9.3.7 reading the eeprom 1. enter jtag instruction prog_commands. 2. enable eeprom read using programming in struction 5a. 3. load address using programming instructions 5b and 5c. 4. read data using programming instruction 5d. 5. repeat steps 3 and 4 until all data have been read. note that the prog_pageread instruction can not be us ed when reading the eeprom. 25.9.3.8 programming the fuses 1. enter jtag instruction prog_commands. 2. enable fuse write using programming instruction 6a. 3. load data high byte using programming instruct ions 6b. a bit valu e of ?0? will program the corresponding fuse, a ?1? will unprogram the fuse. 4. write fuse high byte using programming instruction 6c. 5. poll for fuse write complete using programming instruction 6d, or wait for t wlrh (refer to table 26-15 on page 382 ). 6. load data low byte using programming in structions 6e. a ?0? will program the fuse, a ?1? will unprogram the fuse. 7. write fuse low byte using programming instruction 6f. 8. poll for fuse write complete using programming instruction 6g, or wait for t wlrh (refer to table 26-15 on page 382 ). 364 7679h?can?08/08 at90can32/64/128 25.9.3.9 programmi ng the lock bits 1. enter jtag instruction prog_commands. 2. enable lock bit write using programming instruction 7a. 3. load data using pr ogramming instructions 7b. a bit va lue of ?0? will program the corre- sponding lock bit, a ?1? will leave the lock bit unchanged. 4. write lock bits using programming instruction 7c. 5. poll for lock bit write comp lete using programming instruction 7d, or wait for t wlrh (refer to table 26-15 on page 382 ). 25.9.3.10 reading the fuses and lock bits 1. enter jtag instruction prog_commands. 2. enable fuse/lock bit read using programming instruction 8a. 3. to read all fuses and lock bits, use programming instruction 8f. to only read extended fuse byte , use programming instruction 8b. to only read fuse high byte, use programming instruction 8c. to only read fuse low byte, use programming instruction 8d. to only read lock bits, use programming instruction 8e. 25.9.3.11 reading the signature bytes 1. enter jtag instruction prog_commands. 2. enable signature byte read using programming instruction 9a. 3. load address 0x00 using programming instruction 9b. 4. read first signature byte using programming instruction 9c. 5. repeat steps 3 and 4 with address 0x01 an d address 0x02 to read the second and third signature bytes, respectively. 25.9.3.12 reading the calibration byte 1. enter jtag instruction prog_commands. 2. enable calibration byte read using programming instruction 10a. 3. load address 0x00 using programming instruction 10b. 4. read the calibration byte using programming instruction 10c. 365 7679h?can?08/08 at90can32/64/128 26. electrical characteristics (1) 26.1 absolute maximum ratings* note: 1. electrical characteristics for this product have not yet been finalized. please consider all values listed herein as pre liminary and non-contractual. industrial operating temper ature .......... .........? 40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ....................................? 65c to +150c voltage on any pin except reset with respect to ground .............................. ? 0.5v to v cc +0.5v voltage on reset with respect to ground.... ? 0.5v to +13.0v voltage on v cc with respect to ground............. ? 0.5v to 6.0v dc current per i/o pin ............................................... 40.0 ma dc current v cc and gnd pins................................ 200.0 ma 366 7679h?can?08/08 at90can32/64/128 26.2 dc characteristics t a = -40 c to +85 c, v cc = 2.7v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units v il input low voltage except xtal1 and reset pins ? 0.5 0.2 vcc (1) v v il1 input low voltage xtal1 pin - external clock selected ? 0.5 0.1 vcc (1) v v il2 input low voltage reset pin ? 0.5 0.2 vcc (1) v v ih input high voltage except xtal1 and reset pins 0.6 vcc (2) vcc + 0.5 v v ih1 input high voltage xtal1 pin - external clock selected 0.7 vcc (2) vcc + 0.5 v v ih2 input high voltage reset pin 0.85 vcc (2) vcc + 0.5 v v ol output low voltage (3) (ports a, b, c, d, e, f, g) i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 3v 0.7 0.5 v v oh output high voltage (4) (ports a, b, c, d, e, f, g) i oh = ? 20 ma, v cc = 5v i oh = ? 10 ma, v cc = 3v 4.2 2.4 v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 1.0 a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 1.0 a r rst reset pull-up resistor 30 100 k r pu i/o pin pull-up resistor 20 50 k i cc power supply current active mode (external clock) 8 mhz, v cc = 5v 15 ma 16 mhz, v cc = 5v 29 ma 4 mhz, v cc = 3v 4 ma 8 mhz, v cc = 3v 8 ma power supply current idle mode (external clock) 8 mhz, v cc = 5v 9 ma 16 mhz, v cc = 5v 17 ma 4 mhz, v cc = 3v 3 ma 8 mhz, v cc = 3v 5 ma power supply current power-down mode wdt enabled, v cc = 5v 40 a wdt disabled, v cc = 5v 18 a wdt enabled, v cc = 3v 25 a wdt disabled, v cc = 3v 10 a v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 1.0 8.0 20 mv 367 7679h?can?08/08 at90can32/64/128 notes: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min? means the lowest value where th e pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (20 ma at v cc = 5v, 10 ma at v cc = 3v) under steady state conditions (non-transient), t he following must be observed: tqfp and qfn package: 1] the sum of all iol, for all ports, should not exceed 400 ma. 2] the sum of all iol, for ports a0 - a7, g2, c3 - c7 should not exceed 300 ma. 3] the sum of all iol, for ports c0 - c2, g0 - g1, d0 - d7, xtal2 should not exceed 150 ma. 4] the sum of all iol, for ports b0 - b7, g3 - g4, e0 - e7 should not exceed 150 ma. 5] the sum of all iol, for ports f0 - f7, should not exceed 200 ma. if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (-20 ma at v cc = 5v, -10 ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: tqfp and qfn package: 1] the sum of all i oh , for all ports, should not exceed -400 ma. 2] the sum of all i oh , for ports a0 - a7, g2, c3 - c7 should not exceed -300 ma. 3] the sum of all i oh , for ports c0 - c2, g0 - g1, d0 - d7, xtal2 should not exceed 1-50 ma. 4] the sum of all i oh , for ports b0 - b7, g3 - g4, e0 - e7 should not exceed -150 ma. 5] the sum of all i oh , for ports f0 - f7, should not exceed -200 ma. if i oh exceeds the test condition, v oh may exceed the related specification. pi ns are not guaranteed to source current greater than the listed test condition. 26.3 external clock dr ive characteristics figure 26-1. external clock drive waveforms i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 ? 50 50 na t acid analog comparator propagation delay common mode vcc/2 v cc = 2.7v 170 ns v cc = 5.0v 180 ns t a = -40 c to +85 c, v cc = 2.7v to 5.5v (unless otherwise noted) (continued) symbol parameter condition min. typ. max. units table 26-1. external clock drive symbol parameter v cc = 2.7 - 5.5v v cc = 4.5 - 5.5v units min. max. min. max. 1/t clcl oscillator frequency 0 8 0 16 mhz t clcl clock period 125 62.5 ns t chcx high time 50 25 ns v il1 v ih1 368 7679h?can?08/08 at90can32/64/128 26.4 maximum speed vs. v cc maximum frequency is depending on v cc . as shown in figure 26-2., the maximum frequency vs. v cc curve is linear between 1.8v < v cc < 4.5v. to calculate the maximum frequency at a given voltage in this interval, use this equation: to calculate required voltage for a given frequency, use this equation: at 3 volt, this gives: thus, when v cc = 3v, maximum frequency will be 9.33 mhz. at 8 mhz this gives: thus, a maximum frequency of 8 mhz requires v cc = 2.7v. figure 26-2. maximum frequency vs. v cc , at90can32/64/128 t clcx low time 50 25 ns t clch rise time 1.6 0.5 s t chcl fall time 1.6 0.5 s t clcl change in period from one clock cycle to the next 22% table 26-1. external clock drive (continued) symbol parameter v cc = 2.7 - 5.5v v cc = 4.5 - 5.5v units min. max. min. max. table 26-2. constants used to calculate maximum speed vs. v cc voltage and frequency range a b vx fy 2.7 < vcc < 4.5 or 8 < frequency < 16 8/1.8 1.8/8 2.7 8 frequency avvx ? () fy + ? = voltage bffy ? () vx + ? = frequency 8 1.8 ------- - 32.7 ? () 8 + ? 9.33 == voltage 1.8 8 ------- - 88 ? () 2.7 + ? 2.7 == safe operating area 4.5v 2.7v 5.5v 8 mhz 16 mhz frequency voltage 369 7679h?can?08/08 at90can32/64/128 26.5 two-wire serial in terface characteristics table 26-3 describes the requirements for devices co nnected to the two-wire serial bus. the at90can32/64/128 two-wire serial interface m eets or exceeds these requirements under the noted conditions. timing symbols refer to figure 26-3 . notes: 1. in at90can32/64/128, this parameter is characterized and not 100% tested. table 26-3. two-wire serial bus requirements symbol parameter condition min max units vil input low-voltage ? 0.5 0.3 vcc v vih input high-voltage 0.7 vcc vcc + 0.5 v vhys (1) hysteresis of schmitt trigger inputs 0.05 vcc (2) ?v vol (1) output low-voltage 3 ma sink current 0 0.4 v tr (1) rise time for both sda and scl 20 + 0.1c b (3)(2) 300 ns tof (1) output fall time from v ihmin to v ilmax 10 pf < c b < 400 pf (3) 20 + 0.1c b (3)(2) 250 ns tsp (1) spikes suppressed by input filter 0 50 (2) ns i i input current each i/o pin 0.1 v cc < v i < 0.9 v cc ? 10 10 a c i (1) capacitance for each i/o pin ? 10 pf f scl scl clock frequency f ck (4) > max(16f scl , 250khz) (5) 0 400 khz rp value of pull-up resistor f scl 100 khz f scl > 100 khz t hd;sta hold time (repeated) start condition f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t low low period of the scl clock f scl 100 khz (6) 4.7 ? s f scl > 100 khz (7) 1.3 ? s t high high period of the scl clock f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t su;sta set-up time for a repeated start condition f scl 100 khz 4.7 ? s f scl > 100 khz 0.6 ? s t hd;dat data hold time f scl 100 khz 0 3.45 s f scl > 100 khz 0 0.9 s t su;dat data setup time f scl 100 khz 250 ? ns f scl > 100 khz 100 ? ns t su;sto setup time for stop condition f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t buf bus free time between a stop and start condition f scl 100 khz 4.7 ? s v cc 0,4v ? 3ma ---------------------------- 1000ns c b ------------------- v cc 0,4v ? 3ma ---------------------------- 300ns c b --------------- - 370 7679h?can?08/08 at90can32/64/128 2. required only for f scl > 100 khz. 3. c b = capacitance of one bus line in pf. 4. f ck = cpu clock frequency 5. this requirement applies to all at90can32/64/128 two-wire serial interface operation. other devices connected to the two-wire serial bus need only obey the general f scl requirement. 6. the actual low period generated by the at90can 32/64/128 two-wire serial interface is (1/f scl - 2/f ck ), thus f ck must be greater than 6 mhz for the low time r equirement to be strictly met at f scl = 100 khz. 7. the actual low period generated by the at90can 32/64/128 two-wire serial interface is (1/f scl - 2/f ck ), thus the low time requirement will not be strictly met for f scl > 308 khz when f ck = 8 mhz. still, at90can32/64 /128 devices connected to the bus may communicate at full speed (400 khz) with other at90can32/64/128 devices, as well as any other device with a proper t low acceptance margin. figure 26-3. two-wire serial bus timing 26.6 spi timing characteristics see figure 26-4 and figure 26-5 for details. t su;sta t low t high t low t of t hd;sta t hd;dat t su;dat t su;sto t buf scl sda t r table 26-4. spi timing parameters description mode min. typ. max. 1 sck period master see table 16-4 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5 hold master 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9 ss low to out slave 15 10 sck period slave 4 ? t ck 11 sck high/low (1) slave 2 ? t ck 12 rise/fall time slave 1.6 s 371 7679h?can?08/08 at90can32/64/128 note: in spi programming mode the minimum sck high/low period is: - 2 t clcl for f ck < 12 mhz - 3 t clcl for f ck >12 mhz figure 26-4. spi interface timing requirements (master mode) figure 26-5. spi interface timing requirements (slave mode) 13 setup slave 10 ns 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 2 ? t ck table 26-4. spi timing parameters (continued) description mode min. typ. max. mosi (data output) sck (cpol = 1) miso (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 61 22 3 45 8 7 miso (data output) sck (cpol = 1) mosi (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 17 15 9 x 16 18 372 7679h?can?08/08 at90can32/64/128 26.7 can physical layer characteristics only pads dedicated to the can communi cation belong to the physical layer. notes: 1. characteristics for can physical layer have not yet been finalized. 2. metastable immunity flip-flop. table : can physical layer characteristics (1) parameter condition min. max. units 1 txcan output delay vcc=2.7 v load=20 pf v ol /v oh =v cc / 2 9 ns vcc=4.5 v load=20 pf v ol /v oh =v cc / 2 5.3 2 rxcan input delay vcc=2.7 v v il /v ih =v cc / 2 9 + 1 / f clk io (2) vcc=4.5 v v il /v ih =v cc / 2 7.2 + 1 / f clk io (2) 373 7679h?can?08/08 at90can32/64/128 26.8 adc characteristics notes: 1. values are guidelines only. 2. minimum for av cc is 2.7 v. 3. maximum for av cc is 5.5 v table 26-5. adc characteristics, single ended channels symbol parameter condition min (1) typ (1) max (1) units resolution single ended conversion 10 bits absolute accuracy (included inl, dnl, quantization error, gain and offset error) single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz 1.5 lsb single ended conversion v ref = 4v, vcc = 4v adc clock = 1 mhz lsb single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz noise reduction mode 1.5 lsb single ended conversion v ref = 4v, vcc = 4v adc clock = 1 mhz noise reduction mode lsb integral non-linearity (inl) single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz 0.5 1 lsb differential non-linearity (dnl) single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz 0.3 1 lsb gain error single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz ? 2 0 + 2 lsb offset error single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz ? 2 1 + 2 lsb clock frequency free running conversion 50 1000 khz conversion time free running conversion 65 260 s av cc analog supply voltage v cc ? 0.3 (2) v cc + 0.3 (3) v v ref external reference voltage 2.0 av cc v v in input voltage gnd v ref v input bandwidth 38.5 khz v int internal voltage reference 2.4 2.56 2.7 v r ref reference input resistance 32 k r ain analog input resistance 100 m 374 7679h?can?08/08 at90can32/64/128 notes: 1. values are guidelines only. 2. minimum for av cc is 2.7 v. 3. maximum for av cc is 5.5 v table 26-6. adc characteristics, differential channels symbol parameter condition min (1) typ (1) max (1) units resolution differential conversion gain = 1x or 10x 8bits differential conversion gain = 200x 7bits absolute accuracy gain = 1x, 10x or 200x v ref = 4v, vcc = 5v adc clock = 50 - 200 khz 1lsb integral non-linearity (inl) (accuracy after calibration for offset and gain error) gain = 1x, 10x or 200x v ref = 4v, vcc = 5v adc clock = 50 - 200 khz 0.5 1 lsb gain error gain = 1x, 10x or 200x ? 2 0 + 2 lsb offset error gain = 1x, 10x or 200x v ref = 4v, vcc = 5v adc clock = 50 - 200 khz ? 1 0 + 1 lsb clock frequency free running conversion 50 200 khz conversion time free running conversion 65 260 s av cc analog supply voltage v cc ? 0.3 (2) v cc + 0.3 (3) v v ref external reference voltage differential conversion 2.0 av cc - 0.5 v v in input voltage differential conversion 0 av cc v v diff input differential voltage ?v ref /gain +v ref /gain v adc conversion output ?511 511 lsb input bandwidth differential conversion 4 khz v int internal voltage reference 2.4 2.56 2.7 v r ref reference input resistance 32 k r ain analog input resistance 100 m 375 7679h?can?08/08 at90can32/64/128 26.9 external data memory characteristics notes: 1. this assumes 50% clock duty cycle. the half period is actually the hi gh time of the external clock, xtal1. 2. this assumes 50% clock duty cycle. th e half period is actually the low time of the external clock, xtal1. table 26-7. external data memory characteristics, v cc = 4.5 - 5.5 volts, no wait-state symbol parameter 8 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 1t lhll ale pulse width 115 1.0 t clcl ? 10 ns 2t avll address valid a to ale low 57.5 0.5 t clcl ? 5 (1) ns 3a t llax_st address hold after ale low, write access 55 ns 3b t llax_ld address hold after ale low, read access 55 ns 4t avllc address valid c to ale low 57.5 0.5 t clcl ? 5 (1) ns 5t avrl address valid to rd low 115 1.0 t clcl ? 10 ns 6t avwl address valid to wr low 115 1.0 t clcl ? 10 ns 7t llwl ale low to wr low 47.5 67.5 0.5 t clcl ? 15 (2) 0.5 t clcl + 5 (2) ns 8t llrl ale low to rd low 47.5 67.5 0.5 t clcl ? 15 (2) 0.5 t clcl + 5 (2) ns 9t dvrh data setup to rd high 40 40 ns 10 t rldv read low to data valid 75 1.0 t clcl ? 50 ns 11 t rhdx data hold after rd high 0 0 ns 12 t rlrh rd pulse width 115 1.0 t clcl ? 10 ns 13 t dvwl data setup to wr low 42.5 0.5 t clcl ? 20 (1) ns 14 t whdx data hold after wr high 115 1.0 t clcl ? 10 ns 15 t dvwh data valid to wr high 125 1.0 t clcl ns 16 t wlwh wr pulse width 115 1.0 t clcl ? 10 ns table 26-8. external data memory characteristics, v cc = 4.5 - 5.5 volts, 1 cycle wait-state symbol parameter 8 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 200 2.0 t clcl ? 50 ns 12 t rlrh rd pulse width 240 2.0 t clcl ? 10 ns 15 t dvwh data valid to wr high 240 2.0 t clcl ns 16 t wlwh wr pulse width 240 2.0 t clcl ? 10 ns 376 7679h?can?08/08 at90can32/64/128 table 26-9. external data memory characteristics, v cc = 4.5 - 5.5 volts, srwn1 = 1, srwn0 = 0 symbol parameter 8 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 325 3.0 t clcl ? 50 ns 12 t rlrh rd pulse width 365 3.0 t clcl ? 10 ns 15 t dvwh data valid to wr high 375 3.0 t clcl ns 16 t wlwh wr pulse width 365 3.0 t clcl ? 10 ns table 26-10. external data memory characteristics, v cc = 4.5 - 5.5 volts, srwn1 = 1, srwn0 = 1 symbol parameter 8 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 200 3.0 t clcl ? 50 ns 12 t rlrh rd pulse width 365 3.0 t clcl ? 10 ns 14 t whdx data hold after wr high 240 2.0 t clcl ? 10 ns 15 t dvwh data valid to wr high 375 3.0 t clcl ns 16 t wlwh wr pulse width 365 3.0 t clcl ? 10 ns table 26-11. external data memory characteristics, v cc = 2.7 - 5.5 volts, no wait-state symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 1t lhll ale pulse width 235 t clcl ? 15 ns 2t avll address valid a to ale low 115 0.5 t clcl ? 10 (1) ns 3a t llax_st address hold after ale low, write access 55ns 3b t llax_ld address hold after ale low, read access 55ns 4t avllc address valid c to ale low 115 0.5 t clcl ? 10 (1) ns 5t avrl address valid to rd low 235 1.0 t clcl ? 15 ns 6t avwl address valid to wr low 235 1.0 t clcl ? 15 ns 7t llwl ale low to wr low 115 130 0.5 t clcl ? 10 (2) 0.5 t clcl + 5 (2) ns 8t llrl ale low to rd low 115 130 0.5 t clcl ? 10 (2) 0.5 t clcl + 5 (2) ns 9t dvrh data setup to rd high 45 45 ns 10 t rldv read low to data valid 190 1.0 t clcl ? 60 ns 377 7679h?can?08/08 at90can32/64/128 notes: 1. this assumes 50% clock duty cycle. the half period is actually the hi gh time of the external clock, xtal1. 2. this assumes 50% clock duty cycle. th e half period is actually the low time of the external clock, xtal1. 11 t rhdx data hold after rd high 0 0 ns 12 t rlrh rd pulse width 235 1.0 t clcl ? 15 ns 13 t dvwl data setup to wr low 105 0.5 t clcl ? 20 (1) ns 14 t whdx data hold after wr high 235 1.0 t clcl ? 15 ns 15 t dvwh data valid to wr high 250 1.0 t clcl ns 16 t wlwh wr pulse width 235 1.0 t clcl ? 15 ns table 26-11. external data memory characteristics, v cc = 2.7 - 5.5 volts, no wait-state (continued) symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. table 26-12. external data memory characteristics, v cc = 2.7 - 5.5 volts, srwn1 = 0, srwn0 = 1 symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 440 2.0 t clcl ? 60 ns 12 t rlrh rd pulse width 485 2.0 t clcl ? 15 ns 15 t dvwh data valid to wr high 500 2.0 t clcl ns 16 t wlwh wr pulse width 485 2.0 t clcl ? 15 ns table 26-13. external data memory characteristics, v cc = 2.7 - 5.5 volts, srwn1 = 1, srwn0 = 0 symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 690 3.0 t clcl ? 60 ns 12 t rlrh rd pulse width 735 3.0 t clcl ? 15 ns 15 t dvwh data valid to wr high 750 3.0 t clcl ns 16 t wlwh wr pulse width 735 3.0 t clcl ? 15 ns table 26-14. external data memory characteristics, v cc = 2.7 - 5.5 volts, srwn1 = 1, srwn0 = 1 symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 690 3.0 t clcl ? 60 ns 12 t rlrh rd pulse width 735 3.0 t clcl ? 15 ns 378 7679h?can?08/08 at90can32/64/128 figure 26-6. external memory timing (srwn1 = 0, srwn0 = 0) 14 t whdx data hold after wr high 485 2.0 t clcl ? 15 ns 15 t dvwh data valid to wr high 750 3.0 t clcl ns 16 t wlwh wr pulse width 735 3.0 t clcl ? 15 ns table 26-14. external data memory characteristics, v cc = 2.7 - 5.5 volts, srwn1 = 1, srwn0 = 1 (continued) symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. ale t1 t2 t3 write read wr t4 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 379 7679h?can?08/08 at90can32/64/128 figure 26-7. external memory timing (srwn1 = 0, srwn0 = 1) figure 26-8. external memory timing (srwn1 = 1, srwn0 = 0) ale t1 t2 t3 write read wr t5 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 ale t1 t2 t3 write read wr t6 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 t5 380 7679h?can?08/08 at90can32/64/128 figure 26-9. external memory timing (srwn1 = 1, srwn0 = 1) (1) note: 1. the ale pulse in the last period (t4-t7) is only present if the next instruction accesses the ram (internal or external). 26.10 parallel programming characteristics figure 26-10. parallel programming timing, including some general timing requirements ale t1 t2 t3 write read wr t7 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 t5 t6 data & contol (data, xa0/1, bs1, bs2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl 381 7679h?can?08/08 at90can32/64/128 figure 26-11. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 26-10 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. figure 26-12. parallel programming timing, reading sequence (within the same page) with timing requirements (1) xtal1 pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz 382 7679h?can?08/08 at90can32/64/128 note: 1. the timing requirements shown in figure 26-10 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. notes: 1. t wlrh is valid for the write flash, write eeprom , write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. table 26-15. parallel programming characteristics, v cc = 5v 10% symbol parameter min. typ. max. units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 s t wlrh wr low to rdy/bsy high (1) 3.7 5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 10 ms t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns 383 7679h?can?08/08 at90can32/64/128 27. decoupling capacitors the operating frequency (i.e. system clock) of t he processor determines in 95% of cases the value needed for microcontroller decoupling capacitors. the hypotheses used as first evaluat ion for decoupling capacitors are: ? the operating frequency ( f op ) supplies itself the maximum peak levels of noise. the main peaks are located at f op and 2 ? f op . ? an smc capacitor connected to 2 micro-vias on a pcb has the following characteristics: ? 1.5 nh from the connection of the capacitor to the pcb, ? 1.5 nh from the capaci tor intrinsic inductance. figure 27-1. capacitor description according to the operating frequency of the product, the decoupling capacitances are chosen considering the frequencies to filter, f op and 2 ? f op . the relation between frequencies to cut and decoupling characteristics are defined by: and where: ? l: the inductance equivalent to the global inductance on the vcc/gnd lines. ?c 1 & c 2 : decoupling capacitors (c 1 = 4 ? c 2 ). then, in normalized value range, the decoupling capacitors become: these decoupling capacitors must to be implement ed as close as possible to each pair of power supply pins: ? 21-22 and 52-53 for logic sub-system, ? 64-63 for analogical sub-system. nevertheless, a bulk capacitor of 10-47 f is also needed on the power distribution network of the pcb, near the power source. for further information, please refer to applic ation notes avr040 ?emc design considerations? and avr042 ?hardware design considerations? on the atmel web site. table 27-1. decoupling capacitors vs. frequency f op , operating frequency c 1 c 2 16 mhz 33 nf 10 nf 12 mhz 56 nf 15 nf 10 mhz 82 nf 22 nf 8 mhz 120 nf 33 nf 6 mhz 220 nf 56 nf 4 mhz 560 nf 120 nf pcb capacitor 1.5 nh 0.75 nh 0.75 nh f op 1 2 lc 1 ---------------------- - = 2 f op ? 1 2 lc 2 ---------------------- - = 384 7679h?can?08/08 at90can32/64/128 28. at90can32/64/128 ty pical characteristics ? the following charts show typical behavior. these figures are not tested during manufacturing. all current c onsumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a sine wave generator with rail-to-rail output is used as clock source. ? the power consumption in power-down mo de is independent of clock selection. ? the current consumption is a function of severa l factors such as: operating voltage, operating frequency, loading of i/o pins, switching ra te of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. ? the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switching frequency of i/o pin. ? the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies high er than the ordering code indicates. ? the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog ti mer disabled represents the differential current drawn by the watchdog timer. 28.1 active supply current figure 28-1. active supply current vs. frequency (0.1 - 1.0 mhz) active supply current vs. frequency (25c, 0.1 - 1 mhz) 0 0.5 1 1.5 2 2.5 3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) icc (ma) 5.50v 5.00v 4.50v 4.00v 3.30v 3.00v 2.70v 385 7679h?can?08/08 at90can32/64/128 figure 28-2. active supply current vs . frequency (1 - 16 mhz) figure 28-3. active supply current vs. vc c (internal rc oscillator 8 mhz) active supply current vs. frequency (25c, 1 - 16 mhz) 0 5 10 15 20 25 30 35 40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 frequency (mhz) icc (ma) 5.50v 5.00v 4.50v 4.00v 3.30v 3.00v 2.70v active supply current vs. vcc (internal rc oscillator 8 mhz) 0 2 4 6 8 10 12 14 16 18 20 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ma) 85c 25c -40c 386 7679h?can?08/08 at90can32/64/128 figure 28-4. active supply current vs. vc c (internal rc oscillator 1 mhz) figure 28-5. active supply current vs. vcc (32 khz watch crystal) active supply current vs. vcc (internal rc oscillator 1 mhz) 0 0.5 1 1.5 2 2.5 3 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ma) 85c 25c -40c active supply current vs. vcc (32 khz watch crystal) 0 20 40 60 80 100 120 140 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 25c 387 7679h?can?08/08 at90can32/64/128 28.2 idle supply current figure 28-6. idle supply current vs. frequency (0.1 - 1.0 mhz) figure 28-7. idle supply current vs. frequency (1 - 16 mhz) idle supply current vs. frequency (25c, 0.1 - 1 mhz) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) icc (ma) 5.50v 5.00v 4.50v 4.00v 3.30v 3.00v 2.70v idle supply current vs. frequency (25c, 1 - 16 mhz) 0 5 10 15 20 25 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 frequency (mhz) icc (ma) 5.50v 5.00v 4.50v 4.00v 3.30v 3.00v 2.70v 388 7679h?can?08/08 at90can32/64/128 figure 28-8. idle supply current vs. vcc (internal rc oscillator 8 mhz) figure 28-9. idle supply current vs. vcc (internal rc oscillator 1 mhz) idle supply current vs. vcc (internal rc oscillator 8 mhz) 0 2 4 6 8 10 12 14 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ma) 85c 25c -40c idle supply current vs. vcc (internal rc oscillator 1 mhz) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ma) 85c 25c -40c 389 7679h?can?08/08 at90can32/64/128 figure 28-10. idle supply current vs. vcc (32 khz watch crystal) 28.3 power-down supply current figure 28-11. power-down supply current vs. vcc (watchdog timer disabled) idle supply current vs. vcc (32 khz watch crystal) 0 10 20 30 40 50 60 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 25c power-down supply current vs. vcc (watchdog timer disabled) 0 1 2 3 4 5 6 7 8 9 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 85c 25c -40c 390 7679h?can?08/08 at90can32/64/128 figure 28-12. power-down supply current vs. vcc (watchdog timer enabled) 28.4 power-save supply current figure 28-13. power-save supply current vs. vcc (watchdog timer disabled) power-down supply current vs. vcc (watchdog timer enabled) 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 85c 25c -40c power-save supply current vs. vcc (watch dog timer disabled) 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 25c 391 7679h?can?08/08 at90can32/64/128 28.5 standby supply current figure 28-14. power-save supply current vs. vcc (25c, watchdog timer disabled) 28.6 pin pull-up figure 28-15. i/o pin pull-up resistor current vs. input voltage (vcc = 5v) standby supply current vs. vcc (25c, watchdog timer disabled) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ma) 6 mhz xtal 4 mhz res 2 mhz xtal 2 mhz res i/o pin pull-up resistor current vs. input voltage (vcc = 5v) -160 -140 -120 -100 -80 -60 -40 -20 0 0123456 v io (v) i io (ua) 85c 25c -40c 392 7679h?can?08/08 at90can32/64/128 figure 28-16. i/o pin pull-up resistor current vs. input voltage (vcc = 2.7v) figure 28-17. reset pull-up resistor current vs . reset pin voltage (vcc = 5v) i/o pin pull-up resistor current vs. input voltage (vcc = 2.7v) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.5 1 1.5 2 2.5 3 v io (v) i io (ua) 85c 25c -40c reset pull-up resistor current vs. reset pin voltage (vcc = 5v) -120 -100 -80 -60 -40 -20 0 0123456 v reset (v) i reset (ua) 85c 25c -40c 393 7679h?can?08/08 at90can32/64/128 figure 28-18. reset pull-up resistor current vs . reset pin voltage (vcc = 2.7v) 28.7 pin driver strength figure 28-19. i/o pin source current vs. output voltage (vcc = 5v) reset pull-up resistor current vs. reset pin voltage (vcc = 2.7v) -70 -60 -50 -40 -30 -20 -10 0 0 0.5 1 1.5 2 2.5 3 v reset (v) i reset (ua) 85c 25c -40c i/o pin source current vs. output voltage (vcc = 5v) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 2.5 3 3.5 4 4.5 5 v oh (v) i oh (ma) 85c 25c -40c 394 7679h?can?08/08 at90can32/64/128 figure 28-20. i/o pin source current vs. output voltage (vcc = 2.7v) figure 28-21. i/o pin sink current vs. output voltage (vcc = 5v) i/o pin source current vs. output voltage (vcc = 2.7v) -30 -25 -20 -15 -10 -5 0 0.5 1 1.5 2 2.5 3 v oh (v) i oh (ma) 85c 25c -40c i/o pin sink current vs. output voltage (vcc = 5v) 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 v ol (v) i ol (ma) 85c 25c -40c 395 7679h?can?08/08 at90can32/64/128 figure 28-22. i/o pin sink current vs. output voltage (vcc = 2.7v) 28.8 pin thresholds and hysteresis figure 28-23. i/o input threshold voltage vs. vcc (v ih , i/o pin read as ?1?) i/o pin sink current vs. output voltage (vcc = 2.7v) 0 5 10 15 20 25 30 35 0 0.5 1 1.5 2 2.5 v ol (v) i ol (ma) 85c 25c -40c i/o pin input threshold voltage vs. vcc (vih, i/o pin read as "1") 0.5 0.75 1 1.25 1.5 1.75 2 2.5 3 3.5 4 4.5 5 5.5 vcc (v) threshold (v) 85c 25c -40c 396 7679h?can?08/08 at90can32/64/128 figure 1. i/o input threshold voltage vs. vcc (v il , i/o pin read as ?0?) figure 2. i/o input hysteresis vs. vcc i/o pin input threshold voltage vs. vcc (vil, i/o pin read as "0") 0.5 0.75 1 1.25 1.5 1.75 2 2.5 3 3.5 4 4.5 5 5.5 vcc (v) threshold (v) 85c 25c -40c i/o pin input hysteresis vs. vcc 0 0.1 0.2 0.3 0.4 0.5 0.6 2.533.544.555.5 vcc (v) threshold (v) 85c 25c -40c 397 7679h?can?08/08 at90can32/64/128 28.9 bod thresholds and analog comparator offset figure 28-24. bod thresholds vs. temperature (bod level is 4.1v) figure 28-25. bod thresholds vs. temperature (bod level is 2.7v) bod thresholds vs. temperature (bod level is 4.1v) 3.4 3.6 3.8 4 4.2 4.4 -60 -40 -20 0 20 40 60 80 100 temp (c) threshold (v) rising vcc falling vcc bod thresholds vs. temperature (bod level is 2.7v) 2 2.2 2.4 2.6 2.8 3 -60 -40 -20 0 20 40 60 80 100 temp (c) threshold (v) rising vcc falling vcc 398 7679h?can?08/08 at90can32/64/128 figure 28-26. bandgap voltage vs. operating voltage figure 28-27. analog comparator offset vs. common mode voltage (vcc = 5v) bandgap voltage vs. operating voltage 1.08 1.09 1.1 1.11 1.12 1.13 1.14 2.5 3 3.5 4 4.5 5 5.5 vcc (v) bandgap voltage (v) 85c 25c -40c analog comparator offset vs. common mode voltage (vcc = 5v) -0.002 0 0.002 0.004 0.006 0.008 0.01 0.012 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 common voltage mode (v) comparator offset voltage (v) 85c 25c -40c 399 7679h?can?08/08 at90can32/64/128 28.10 internal oscillator speed figure 28-28. watchdog oscillator freque ncy vs. operating voltage figure 28-29. calibrated 8 mhz rc oscillato r frequency vs. temperature watchdog oscillator frequency vs. vcc 800 850 900 950 1000 1050 1100 1150 1200 2.5 3 3.5 4 4.5 5 5.5 vcc (v) f watchdog (khz) 85c 25c -40c calibrated 8mhz rc oscillator frequency vs. temperature 7.2 7.4 7.6 7.8 8 8.2 8.4 8.6 8.8 -60 -40 -20 0 20 40 60 80 100 temp (c) f rc (mhz) 2.7v 4.0v 5.5v 400 7679h?can?08/08 at90can32/64/128 figure 28-30. calibrated 8 mhz rc oscillator fr equency vs. operating voltage figure 28-31. calibrated 8 mhz rc oscillator frequency vs. osccal value calibrated 8mhz rc oscillator frequency vs. vcc 6 6.5 7 7.5 8 8.5 9 9.5 10 2.5 3 3.5 4 4.5 5 5.5 vcc (v) f rc (mhz) 85c 25c -40c calibrated 8mhz rc oscillator frequency vs. osccal value 4 5 6 7 8 9 10 11 12 13 14 15 16 0 163248648096112128 osccal value f rc (mhz) 85c 25c -40c 401 7679h?can?08/08 at90can32/64/128 28.11 current consumpti on of peripheral units figure 28-32. brownout detector current vs. operating voltage figure 28-33. adc current vs. operating voltage (adc at 1 mhz) brownout detector current vs. vcc 5 10 15 20 25 30 35 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 85c 25c -40c adc current vs. vcc (adc at 1 mhz) 0 50 100 150 200 250 300 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 85c 25c -40c 402 7679h?can?08/08 at90can32/64/128 figure 28-34. aref external reference cu rrent vs. operating voltage figure 28-35. analog comparator current vs. operating voltage aref external reference current vs. vcc 40 60 80 100 120 140 160 180 200 2.5 3 3.5 4 4.5 5 5.5 vcc (v) i aref (ua) 85c 25c -40c analog comparator current vs. vcc 0 20 40 60 80 100 120 2.5 3 3.5 4 4.5 5 5.5 vcc (v) i cc (ua) 85c 25c -40c 403 7679h?can?08/08 at90can32/64/128 figure 28-36. programming current vs. operating voltage 28.12 current consumption in reset and reset pulse width figure 28-37. reset supply current vs. operating voltage (0.1 - 1.0 mhz) (excluding current through the reset pull-up) programming current vs. vcc 0 5 10 15 20 25 2.5 3 3.5 4 4.5 5 5.5 vcc (v) i cc (ma) 85c 25c -40c reset supply current vs. frequency (25c, 0.1 - 1 mhz) ( excluding current through the reset pull- up) 0 0.05 0.1 0.15 0.2 0.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) icc (ma) 5.50v 5.00v 4.50v 4.00v 3.30v 3.00v 2.70v 404 7679h?can?08/08 at90can32/64/128 figure 28-38. reset supply current vs. operating voltage (1 - 16 mhz) (excluding current through the reset pull-up) figure 28-39. minimum reset pulse width vs. operating voltage reset supply current vs. frequency (1 - 16 mhz) (excluding current through the reset pull-up) 0 0.5 1 1.5 2 2.5 3 3.5 01234567891011121314151617 frequency (mhz) icc (ma) 5.50v 5.00v 4.50v 4.00v 3.30v 3.00v 2.70v minimum reset pulse width vs. vcc 0 250 500 750 1000 1250 1500 2.5 3 3.5 4 4.5 5 5.5 vcc (v) pulse width (ns) 85c 25c -40c 405 7679h?can?08/08 at90can32/64/128 29. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved (0xfe) reserved (0xfd) reserved (0xfc) reserved (0xfb) reserved (0xfa) canmsg msg 7 msg 6 msg 5 msg 4 msg 3 msg 2 msg 1 msg 0 page 266 (0xf9) canstmh timstm15 timstm14 timstm13 timstm12 timstm11 timstm10 timstm9 timstm8 page 266 (0xf8) canstml timstm7 timstm6 timstm5 timstm4 timstm3 timstm2 timstm1 timstm0 page 266 (0xf7) canidm1 idmsk 28 idmsk 27 idmsk 26 idmsk 25 idmsk 24 idmsk 23 idmsk 22 idmsk 21 page 265 (0xf6) canidm2 idmsk 20 idmsk 19 idmsk 18 idmsk 17 idmsk 16 idmsk 15 idmsk 14 idmsk 13 page 265 (0xf5) canidm3 idmsk 12 idmsk 11 idmsk 10 idmsk 9 idmsk 8 idmsk 7 idmsk 6 idmsk 5 page 265 (0xf4) canidm4 idmsk 4 idmsk 3 idmsk 2 idmsk 1 idmsk 0rtrmsk ?idemsk page 265 (0xf3) canidt1 idt 28 idt 27 idt 26 idt 25 idt 24 idt 23 idt 22 idt 21 page 263 (0xf2) canidt2 idt 20 idt 19 idt 18 idt 17 idt 16 idt 15 idt 14 idt 13 page 263 (0xf1) canidt3 idt 12 idt 11 idt 10 idt 9 idt 8 idt 7 idt 6 idt 5 page 263 (0xf0) canidt4 idt 4 idt 3 idt 2 idt 1 idt 0 rtrtag rb1tag rb0tag page 263 (0xef) cancdmob conmob1 conmob0 rplv ide dlc3 dlc2 dlc1 dlc0 page 262 (0xee) canstmob dlcw txok rxok berr serr cerr ferr aerr page 261 (0xed) canpage mobnb3 mobnb2 mobnb1 mobnb0 ainc indx2 indx1 indx0 page 260 (0xec) canhpmob hpmob3 hpmob2 hpmob1 hp mob0 cgp3 cgp2 cgp1 cgp0 page 260 (0xeb) canrec rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 page 260 (0xea) cantec tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 page 260 (0xe9) canttch timttc15 timttc14 timttc13 timttc12 timttc11 timttc10 timttc9 timttc8 page 260 (0xe8) canttcl timttc7 timttc6 timttc5 timttc4 timttc3 timttc2 timttc1 timttc0 page 260 (0xe7) cantimh cantim15 cantim14 cantim13 cantim12 cantim11 cantim10 cantim9 cantim8 page 259 (0xe6) cantiml cantim7 cantim6 cantim5 cantim4 cantim3 cantim2 cantim1 cantim0 page 259 (0xe5) cantcon tprsc7 tprsc6 tprsc5 tprsc4 tprsc3 tprsc2 trpsc1 tprsc0 page 259 (0xe4) canbt3 ? phs22 phs21 phs20 phs12 phs11 phs10 smp page 258 (0xe3) canbt2 ? sjw1 sjw0 ? prs2 prs1 prs0 ? page 258 (0xe2) canbt1 ? brp5 brp4 brp3 brp2 brp1 brp0 ? page 257 (0xe1) cansit1 ? sit14 sit13 sit12 sit11 sit10 sit9 sit8 page 257 (0xe0) cansit2 sit7 sit6 sit5 sit4 sit3 sit2 sit1 sit0 page 257 (0xdf) canie1 ? iemob14 iemob13 iemob12 iemob11 iemob10 iemob9 iemob8 page 257 (0xde) canie2 iemob7 iemob6 iemob5 iemob4 iemob3 iemob2 iemob1 iemob0 page 257 (0xdd) canen1 ? enmob14 enmob13 enmob12 enmob11 enmob10 enmob9 enmob8 page 256 (0xdc) canen2 enmob7 enmob6 enmob5 enmob4 enmob3 enmob2 enmob1 enmob0 page 256 (0xdb) cangie enit enboff enrx entx enerr enbx energ enovrt page 255 (0xda) cangit canit boffit ovrtim bxok serg cerg ferg aerg page 254 (0xd9) cangsta ?ovrg ? txbsy rxbsy enfg boff errp page 253 (0xd8) cangcon abrq ovrq ttc synttc listen test ena/stb swres page 252 (0xd7) reserved (0xd6) reserved (0xd5) reserved (0xd4) reserved (0xd3) reserved (0xd2) reserved (0xd1) reserved (0xd0) reserved (0xcf) reserved (0xce) udr1 udr17 udr16 udr15 udr14 udr13 udr12 udr11 udr10 page 195 (0xcd) ubrr1h ? ? ? ? ubrr111 ubrr110 ubrr19 ubrr18 page 199 (0xcc) ubrr1l ubrr17 ubrr16 ubrr15 ubrr14 ubrr13 ubrr12 ubrr11 ubrr10 page 199 (0xcb) reserved (0xca) ucsr1c ? umsel1 upm11 upm10 usbs1 ucsz11 ucsz10 ucpol1 page 198 (0xc9) ucsr1b rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 page 197 (0xc8) ucsr1a rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 page 195 (0xc7) reserved (0xc6) udr0 udr07 udr06 udr05 udr04 udr03 udr02 udr01 udr00 page 195 (0xc5) ubrr0h ? ? ? ? ubrr011 ubrr010 ubrr09 ubrr08 page 199 (0xc4) ubrr0l ubrr07 ubrr06 ubrr05 ubrr04 ubrr03 ubrr02 ubrr01 ubrr00 page 199 (0xc3) reserved (0xc2) ucsr0c ? umsel0 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 page 197 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 page 196 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 page 195 (0xbf) reserved 406 7679h?can?08/08 at90can32/64/128 (0xbe) reserved (0xbd) reserved (0xbc) twcr twint twea twsta twsto twwc twen ?twie page 212 (0xbb) twdr twdr7 twdr6 twdr5 twdr4 twdr3 twdr2 twdr1 twdr0 page 214 (0xba) twar twar6 twar5 twar4 twar3 twar2 twar1 twar0 twgce page 214 (0xb9) twsr tws7 tws6 tws5 tws4 tws3 ?twps1twps0 page 213 (0xb8) twbr twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 page 212 (0xb7) reserved (0xb6) assr ? ? ? exclk as2 tcn2ub ocr2ub tcr2ub page 160 (0xb5) reserved (0xb4) reserved (0xb3) ocr2a ocr2a7 ocr2a6 ocr2a5 ocr2a4 ocr2a3 ocr2a2 ocr2a1 ocr2a0 page 159 (0xb2) tcnt2 tcnt27 tcnt26 tcnt25 tcnt24 tcnt23 tcnt22 tcnt21 tcnt20 page 159 (0xb1) reserved (0xb0) tccr2a foc2a wgm20 com2a1 com2 a0 wgm21 cs22 cs21 cs20 page 164 (0xaf) reserved (0xae) reserved (0xad) reserved (0xac) reserved (0xab) reserved (0xaa) reserved (0xa9) reserved (0xa8) reserved (0xa7) reserved (0xa6) reserved (0xa5) reserved (0xa4) reserved (0xa3) reserved (0xa2) reserved (0xa1) reserved (0xa0) reserved (0x9f) reserved (0x9e) reserved (0x9d) ocr3ch ocr3c15 ocr3c14 ocr3c13 ocr3c12 ocr3c11 ocr3c10 ocr3c9 ocr3c8 page 141 (0x9c) ocr3cl ocr3c7 ocr3c6 ocr3c5 ocr3c4 ocr3c3 ocr3c2 ocr3c1 ocr3c0 page 141 (0x9b) ocr3bh ocr3b15 ocr3b14 ocr3b13 ocr3b12 ocr3b11 ocr3b10 ocr3b9 ocr3b8 page 141 (0x9a) ocr3bl ocr3b7 ocr3b6 ocr3b5 ocr3b4 ocr3b3 ocr3b2 ocr3b1 ocr3b0 page 141 (0x99) ocr3ah ocr3a15 ocr3a14 ocr3a13 ocr3a12 ocr3a11 ocr3a10 ocr3a9 ocr3a8 page 141 (0x98) ocr3al ocr3a7 ocr3a6 ocr3a5 ocr3a4 ocr3a3 ocr3a2 ocr3a1 ocr3a0 page 141 (0x97) icr3h icr315 icr314 icr313 icr312 icr311 icr310 icr39 icr38 page 142 (0x96) icr3l icr37 icr36 icr35 icr34 icr33 icr32 icr31 icr30 page 142 (0x95) tcnt3h tcnt315 tcnt314 tcnt313 tcnt312 tcnt311 tcnt310 tcnt39 tcnt38 page 140 (0x94) tcnt3l tcnt37 tcnt36 tcnt35 tcnt34 tcnt33 tcnt32 tcnt31 tcnt30 page 140 (0x93) reserved (0x92) tccr3c foc3a foc3b foc3c ? ? ? ? page 140 (0x91) tccr3b icnc3 ices3 ? wgm33 wgm32 cs32 cs31 cs30 page 138 (0x90) tccr3a com3a1 com3a0 com3b1 com3b0 com3c1 com3c0 wgm31 wgm30 page 135 (0x8f) reserved (0x8e) reserved (0x8d) ocr1ch ocr1c15 ocr1c14 ocr1c13 ocr1c12 ocr1c11 ocr1c10 ocr1c9 ocr1c8 page 141 (0x8c) ocr1cl ocr1c7 ocr1c6 ocr1c5 ocr1c4 ocr1c3 ocr1c2 ocr1c1 ocr1c0 page 141 (0x8b) ocr1bh ocr1b15 ocr1b14 ocr1b13 ocr1b12 ocr1b11 ocr1b10 ocr1b9 ocr1b8 page 141 (0x8a) ocr1bl ocr1b7 ocr1b6 ocr1b5 ocr1b4 ocr1b3 ocr1b2 ocr1b1 ocr1b0 page 141 (0x89) ocr1ah ocr1a15 ocr1a14 ocr1a13 ocr1a12 ocr1a11 ocr1a10 ocr1a9 ocr1a8 page 141 (0x88) ocr1al ocr1a7 ocr1a6 ocr1a5 ocr1a4 ocr1a3 ocr1a2 ocr1a1 ocr1a0 page 141 (0x87) icr1h icr115 icr114 icr113 icr112 icr111 icr110 icr19 icr18 page 142 (0x86) icr1l icr17 icr16 icr15 icr14 icr13 icr12 icr11 icr10 page 142 (0x85) tcnt1h tcnt115 tcnt114 tcnt113 tcnt112 tcnt111 tcnt110 tcnt19 tcnt18 page 140 (0x84) tcnt1l tcnt17 tcnt16 tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 page 140 (0x83) reserved (0x82) tccr1c foc1a foc1b foc1c ? ? ? ? ? page 139 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 page 138 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 com1c1 com1c0 wgm11 wgm10 page 135 (0x7f) didr1 ? ? ? ? ? ?ain1dain0d page 272 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d page 292 (0x7d) reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 407 7679h?can?08/08 at90can32/64/128 (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 page 287 (0x7b) adcsrb ?acme ? ? ? adts2 adts1 adts0 page 291 , 269 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 page 289 (0x79) adch - / adc9 - / adc8 - / adc7 - / adc6 - / adc5 - / adc4 adc9 / adc3 adc8 / adc2 page 290 (0x78) adcl adc7 / adc1 adc6 / adc0 adc5 / - adc4 / - adc3 / - adc2 / - adc1 / - adc0 / page 290 (0x77) reserved (0x76) reserved (0x75) xmcrb xmbk ? ? ? ? xmm2 xmm1 xmm0 page 33 (0x74) xmcra sre srl2 srl1 srl0 srw11 srw10 srw01 srw00 page 32 (0x73) reserved (0x72) reserved (0x71) timsk3 ? ?icie3 ? ocie3c ocie3b ocie3a toie3 page 142 (0x70) timsk2 ? ? ? ? ? ? ocie2a toie2 page 162 (0x6f) timsk1 ? ?icie1 ? ocie1c ocie1b ocie1a toie1 page 142 (0x6e) timsk0 ? ? ? ? ? ? ocie0a toie0 page 112 (0x6d) reserved (0x6c) reserved (0x6b) reserved (0x6a) eicrb isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 page 94 (0x69) eicra isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 page 93 (0x68) reserved (0x67) reserved (0x66) osccal ? cal6 cal5 cal4 cal3 cal2 cal1 cal0 page 42 (0x65) reserved (0x64) reserved (0x63) reserved (0x62) reserved (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 page 44 (0x60) wdtcr ? ? ? wdce wde wdp2 wdp1 wdp0 page 58 0x3f (0x5f) sreg ithsvnz c page 11 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 page 14 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 14 0x3c (0x5c) reserved 0x3b (0x5b) rampz (1) ? ? ? ? ? ? ? rampz0 page 13 0x3a (0x5a) reserved 0x39 (0x59) reserved 0x38 (0x58) reserved 0x37 (0x57) spmcsr spmie rwwsb ? rwwsre blbset pgwrt pgers spmen page 326 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr jtd ? ?pud ? ? ivsel ivce page 64 , 73 , 304 0x34 (0x54) mcusr ? ? ? jtrf wdrf borf extrf porf page 56 , 304 0x33 (0x53) smcr ? ? ? ?sm2sm1sm0se page 46 0x32 (0x52) reserved 0x31 (0x51) ocdr idrd/ocdr7 ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr0 page 299 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 page 270 0x2f (0x4f) reserved 0x2e (0x4e) spdr spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 page 175 0x2d (0x4d) spsr spif wcol ? ? ? ? ?spi2x page 175 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 page 173 0x2b (0x4b) gpior2 gpior27 gpior26 gpior25 gpior24 gpior23 gpior22 gpior21 gpior20 page 36 0x2a (0x4a) gpior1 gpior17 gpior16 gpior15 gpior14 gpior13 gpior12 gpior11 gpior10 page 36 0x29 (0x49) reserved 0x28 (0x48) reserved 0x27 (0x47) ocr0a ocr0a7 ocr0a6 ocr0a5 ocr0a4 ocr0a3 ocr0a2 ocr0a1 ocr0a0 page 112 0x26 (0x46) tcnt0 tcnt07 tcnt06 tcnt05 tcnt04 tcnt03 tcnt02 tcnt01 tcnt00 page 111 0x25 (0x45) reserved 0x24 (0x44) tccr0a foc0a wgm00 com0a1 com0 a0 wgm01 cs02 cs01 cs00 page 109 0x23 (0x43) gtccr tsm ? ? ? ? ? psr2 psr310 page 98 , 164 0x22 (0x42) eearh (2) ? ? ? ? eear11 eear10 eear9 eear8 page 22 0x21 (0x41) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 page 22 0x20 (0x40) eedr eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 page 23 0x1f (0x3f) eecr ? ? ? ? eerie eemwe eewe eere page 23 0x1e (0x3e) gpior0 gpior07 gpior06 gpior05 gpior04 gpior03 gpior02 gpior01 gpior00 page 36 0x1d (0x3d) eimsk int7 int6 int5 int4 int3 int2 int1 int0 page 95 0x1c (0x3c) eifr intf7 intf6 intf5 intf4 intf3 intf2 intf1 intf0 page 95 0x1b (0x3b) reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 408 7679h?can?08/08 at90can32/64/128 notes: 1. address bits exceeding pcmsb ( table 25-11 on page 341 ) are don?t care. 2. address bits exceeding eeamsb ( table 25-12 on page 341 ) are don?t care. 3. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. 4. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 5. some of the status flags are cleared by writing a logical one to them. note that , unlike most other avrs, the cbi and sbi instructions will only operate on the specified bit, and can th erefore be used on registers containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 6. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the at90can32/64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1a (0x3a) reserved 0x19 (0x39) reserved 0x18 (0x38) tifr3 ? ?icf3 ? ocf3c ocf3b ocf3a tov3 page 143 0x17 (0x37) tifr2 ? ? ? ? ? ?ocf2atov2 page 162 0x16 (0x36) tifr1 ? ?icf1 ? ocf1c ocf1b ocf1a tov1 page 143 0x15 (0x35) tifr0 ? ? ? ? ? ?ocf0atov0 page 112 0x14 (0x34) portg ? ? ? portg4 portg3 portg2 portg1 portg0 page 92 0x13 (0x33) ddrg ? ? ? ddg4 ddg3 ddg2 ddg1 ddg0 page 92 0x12 (0x32) ping ? ? ? ping4 ping3 ping2 ping1 ping0 page 92 0x11 (0x31) portf portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 page 91 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 page 91 0x0f (0x2f) pinf pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 page 92 0x0e (0x2e) porte porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 page 91 0x0d (0x2d) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 page 91 0x0c (0x2c) pine pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 page 91 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 page 91 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 page 91 0x09 (0x29) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 page 91 0x08 (0x28) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 page 90 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 page 90 0x06 (0x26) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 page 90 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 page 90 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 90 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 90 0x02 (0x22) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 page 89 0x01 (0x21) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 page 90 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 page 90 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 409 7679h?can?08/08 at90can32/64/128 30. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 410 7679h?can?08/08 at90can32/64/128 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 elpm extended load program memory r0 (rampz:z) none 3 elpm rd, z extended load program memory rd (rampz:z) none 3 elpm rd, z+ extended load program memory and post-inc rd (rampz:z), rampz:z rampz:z+1 none 3 spm store program memory (z) r1:r0 none - mnemonics operands description operation flags #clocks 411 7679h?can?08/08 at90can32/64/128 in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks 412 7679h?can?08/08 at90can32/64/128 31. ordering information notes: 1. these devices can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering in forma- tion and minimum quantities. 32. packaging information ordering code (1) speed (mhz) power supply (v) package operation range product marking at90can32-16ai 16 2.7 - 5.5 a2 64 industrial (-40 to +85c) at90can32-16ai at90can32-16mi 16 2.7 - 5.5 z64-1 industrial (-40 to +85c) at90can32-16mi at90can32-16au 16 2.7 - 5.5 a2 64 industrial (-40 to +85c) green at90can32-16au at90can32-16mu 16 2.7 - 5.5 z64-1 industrial (-40 to +85c) green at90can32-16mu at90can64-16ai 16 2.7 - 5.5 a2 64 industrial (-40 to +85c) at90can64-16ai at90can64-16mi 16 2.7 - 5.5 z64-2 industrial (-40 to +85c) at90can64-16mi at90can64-16au 16 2.7 - 5.5 a2 64 industrial (-40 to +85c) green at90can64-16au at90can64-16mu 16 2.7 - 5.5 z64-2 industrial (-40 to +85c) green at90can64-16mu at90can128-16ai 16 2.7 - 5.5 a2 64 industrial (-40 to +85c) at90can128-16ai at90can128-16mi 16 2.7 - 5.5 z64-2 industrial (-40 to +85c) at90can128-16mi at90can128-16au 16 2.7 - 5.5 a2 64 industrial (-40 to +85c) green at90can128-16au at90can128-16mu 16 2.7 - 5.5 z64-2 industrial (-40 to +85c) green at90can128-16mu package type a2 64 64-lead, thin (1.0 mm / 0.03937 in) plastic gull wing quad flat package. z64-1 64-lead, qfn, exposed die attach pad d2 /e2: 5.4 0.1mm / 0.212 0.004 in. z64-2 64-lead, qfn, exposed die attach pad d2 /e2: 6.0 0.1mm / 0.236 0.004 in. 413 7679h?can?08/08 at90can32/64/128 32.1 tqfp64 64 pins thin quad flat pack side view a c j l 0 o to 7 o top view 1 64 e1 e d e f 11 o / 13 o 0.100 mm lead coplanarity a2 a - - - - 1.20 - - - - 0.047 a2 0.95 1.05 0.037 0.041 c d 0.09 0.20 0.004 0.008 min mm max inch 16.00 bsc 0.630 bsc j 0.05 0.15 0.002 0.006 f 0.30 0.45 0.012 0.018 l e 0.45 0.75 0.018 0.030 0.80 bsc 0.0315 bsc d1 14.00 bsc 0.551 bsc e 16.00 bsc 0.630 bsc e1 14.00 bsc 0.551 bsc min max drawings not scaled 414 7679h?can?08/08 at90can32/64/128 32.2 qfn64 415 7679h?can?08/08 at90can32/64/128 416 7679h?can?08/08 at90can32/64/128 33. errata 33.1 errata summary 33.1.1 at90can32 revb (date code 0107) ? can acknowledge error in 3-sample mode with prescaler =1 ? can transmission af ter 3-bit intermission ? asynchronous timer-2 wakes up without interrupt 33.1.2 at90can32 reva (date code < 0107) ? can acknowledge error in 3-sample mode with prescaler =1 ? can transmission af ter 3-bit intermission ? asynchronous timer-2 wakes up without interrupt ? reset of timer-2 flags in asynchronous mode ? miss-functioning when code stack is in xram 33.1.3 at90can64 reva ? lpm instruction versus prot ection levels and bootsize ? can acknowledge error in 3-sample mode with prescaler =1 ? can transmission af ter 3-bit intermission ? asynchronous timer-2 wakes up without interrupt 33.1.4 at90can128 revd (date code 0107) ? can acknowledge error in 3-sample mode with prescaler =1 ? can transmission af ter 3-bit intermission ? asynchronous timer-2 wakes up without interrupt 33.1.5 at90can128 revc (date code < 4006) ? can acknowledge error in 3-sample mode with prescaler =1 ? can transmission af ter 3-bit intermission ? asynchronous timer-2 wakes up without interrupt ? reset of timer-2 flags in asynchronous mode ? miss-functioning when code stack is in xram ? extra consumption in power reduction modes ? power supply current in power-down mode 33.2 errata description 8. at90can64 : lpm instruction versus protection levels and bootsize in at90can64 product, if the bootloader and application protection modes are pro- grammed at level 3, the lpm instruction does not operate properly in some configuration cases. it will not load the right constant value. the differents cases versus bootsize value and flash memory areas are detailed in following tables : 417 7679h?can?08/08 at90can32/64/128 let?s consider 4 sections in the flash, described below: failing cases : problem fix / workaround if protection level 3 is mandatory, the lpm instruction must be mo ved outside the failing sections. 7. can acknowledge error in 3-sample mode with prescaler =1 some acknowledge errors can occur when the clock prescaler = 1 (brp[5..0] = 0 in canbtr1 register) and the smp bit is set (canbtr3[0] = 1 in canbtr3 register). that can result in a reduction of the maximum length of the can bus. problem fix / workaround if brp[5..0]=0 use smp=0. 6. can transmission after 3-bit intermission if a transmit message object (mob) is enabl ed while the can bus is busy with an on going message, the transmitter will wait for the 3-bit intermission before starting its transmission. this is in full agreement with the can recommendation. if the transmitter lost arbitration against another node, two conditions can occur: - at least one receive mob of the chip are programmed to accept the incoming message. in this case, the transmitter will wait for the next 3-bit intermission to re try its transmission. - no receive mob of the chip are programmed to accept the incoming message. in this case the transmitter will wait for a 4-bit intermissio n to retry its transmi ssion. in this case, any other can nodes ready to transmit after a 3-bi t intermission will star t transmit before the chip transmitter, even if their messages have lower priority ids. problem fix / workaround always have a receive mob enabled ready to accept any incoming messages. thanks to the implementation of the can interface, a receive mob must be enable at latest, before the 1 st bit of the dlc field. the receive mob status register is written (rxok if message ok) immediately after t he 6th bit of the end of frame field. this will leave in can2.0a mode a minimum 19-bit time delay to respond to the end of message interrupt (rxok) and re- enable the receive mob before the start of the dlc field of the next incoming message. this table 33-1. flash memory sections memory space a : application memory space b : application memory space c : application memory space d : bootloader bootsize=4096 words 0000h-2fffh 3000h-3fffh 4000h-6fffh 7000h-7fffh bootsize=2048 words 0000h-37ffh 3800h-3fffh 4000h-77ffh 7800h-7fffh bootsize=1024 words 0000h-3bffh 3c00h-3fffh 4000h-7bffh 7c00h-7fffh bootsize=512 words 0000h-3dffh 3e00h-3fffh 4000h-7dffh 7e00h-7fffh from memory space to memeory space bug comment lpm instruction d b allowed but should not be valid lpm instruction b d allowed but should not be valid lpm instruction b a or c not allowed but should be lpm instruction a or c b not allowed but should be 418 7679h?can?08/08 at90can32/64/128 minimum delay will be 39-bit time in can2 .0b. see can2.0a can2.0b frame timings below. workaround implementation the workaround is to have the last mob (mob14) as "spy" enabled all the time; it is the mob of lowest priority. if a mob other than mob1 4 is programmed in receive mode and its accep- tance filter matches with the incoming message id, th is mob will take the message. mob14 will only take messages than no other mobs will have acce pted. mob14 will need to be re- enabled fast enough to manage back to back frames. the deadline to do this is the begin- ning of dlc slot of incoming frames as explained above. minimum code to insert in can interrupt routine: __interrupt void can_int_handler(void) { if ((cansit1 & 0x40) == 0x40 ) /* mob14 interrupt (sit14=1) */ { canpage = (0x0e << 4); /* select mob14 */ canstmob = 0x00; /* reset mob14 status */ cancdmob = 0x88; /* reception enable */ } ........ ........ } 5. asynchronous timer-2 wakes up without interrupt the asynchronous timer can wake from sleep wit hout giving interrupt. the error only occurs if the interrupt flag(s) is cleared by software less than 4 cycles before going to sleep and this clear is done exactly when it is supposed to be set (compare match or overflow). only the interrupts flags are affected by the clear, not the signal witch is used to wake up the part. problem fix / workaround no known workaround, try to lock the code to avoid such a timing. can 2.0a 19-bit time minimum t 1 (rxok) t 2 arbitration field control field end of frame crc field ack field inter- mission 11-bit identifier id10..0 crc del. ack del. 15-bit crc sof sof rtr ide r0 ack 7 bits 4-bit dlc dlc4..0 3 bits can 2.0b 39-bit time minimum t 1 (rxok) t 2 end of frame crc field ack field inter- mission arbitration field control field crc del. ack del. 15-bit crc sof sof ack 7 bits 3 bits 11-bit base identifier idt28..18 18-bit identifier extension id17..0 4-bit dlc dlc4..0 srr ide r0 rtr r1 419 7679h?can?08/08 at90can32/64/128 4. reset of timer-2 flags in asynchronous mode in asynchronous mode, a wr iting in any regist er of the timer-2 (tccr2a, tcnt2 & ocr2a) automatically clears tov2 and ocf2a flags in tfir register. problem fix / workaround ? tov2: do not write in timer-2 registers if tcnt2 is equal to 0xff, 0x00 or 0x01. ? ocf2a: do not write in timer-2 registers if tcnt2 and ocr2a differ from -1, 0 or 1. 3. miss-functioning when code stack is in xram if the stack pointer (sp) targets the xram and if the execution of an instruction is split to serve a rising interrupt, the last operation of th is instruction, executed after pushing out the return address from xram, may be disturbed providing wrong data to the system. example: - the ?out? instruction can be executed twice - the ?mov? instruction can update a register with un-predictable data. problem fix / workaround map the code stack in internal sram. 2. extra consumption in power reduction modes when avcc is selected as voltage reference for adc (ref[1,0]=0,1), an extra consumption close to 30 a (5.0v/25c) appears in power reduction modes. problem fix / workaround switch from avcc to aref pin (ref[1,0]=0, 0) before enabling one of the power reduction modes. 1. power supply current in power-down mode the power supply current in power-down mode of at90can128 parts with lot number before a04900 is: t a = - 40c to + 85c symbol parameter condition min. typ. max. max. i cc power supply current power-down mode wdt enabled, v cc = 5 v 150 a wdt disabled, v cc = 5 v 120 a wdt enabled, v cc = 3 v 50 a wdt disabled, v cc = 3 v 40 a 420 7679h?can?08/08 at90can32/64/128 34. datasheet revision history for at90can32/64/128 please note that the page numbers in this section refer to this document. the revision noted in this section refer to the document revision. 34.1 changes from 7679g - 03/08 to 7679h - 08/08 1. minor corrections throughout the document. 34.2 changes from 7679f - 11/07 to 7679g - 03/08 1. added errata problem 8 on 416 . 34.3 changes from 7679e - 07/07 to 7679f - 11/07 1. updated ?errata? on page 416 . 2. updated ?bit 0 ? smp: sample point(s)? on page 259 in section ?can register description? 34.4 changes from 7679d - 02/07 to 7679e - 07/07 1. more details on canstmob register. section 19.11.1 on page 261 . 2. update to ordering information, product marking. section 32. on page 412 . 34.5 changes from 7679c - 01/07 to 7679d - 02/07 1. modified dc characteristics - icc active & idle modes. section 26.2 on page 366 . 2. removed ?spi programming timing? erra ta and replaced by the note in the 4 th step of ?spi serial programming? on page 349 . 3. updated ?bit 1 ? ena/stb: enable / standby mode? on page 252 in section ?can reg- ister description? 4. updated por characteristics in table 7-1 on page 52 . 5. updated ?phase correct pwm mode? on page 153 . 6. updated spi features . section 16.1 on page 168 . 7. updated ?errata? on page 416 . 34.6 changes from 7679b - 11/06 to 7679c - 01/07 1. modified qfn64 package drawing. section 32.2 on page 414 and section 32. on page 412 . 34.7 changes from 7679a - 10/06 to 7679b - 11/06 1. can sampling point position when the prescaler is bypassed in section 19.4.3 ?baud rate? on page 242 and update of table 19-2 on page 267 . 34.8 document creation 1. 7679a - 10/06 421 7679h?can?08/08 at90can32/64/128 features .............. ................ ................ ............... .............. .............. ............ 1 1 description ............ .............. .............. ............... .............. .............. ............ 2 1.1 comparison between at90can32, at 90can64 and at90can128 ................2 1.2 part description ..................................................................................................2 1.3 disclaimer ...........................................................................................................3 1.4 block diagram ....................................................................................................4 1.5 pin configurations ..............................................................................................5 1.6 pin descriptions ..................................................................................................6 2 about code examples ........ .............. ............... .............. .............. ............ 8 3 avr cpu core ................. ................ ................. .............. .............. ............ 9 3.1 introduction .........................................................................................................9 3.2 architectural overview ........................................................................................9 3.3 alu ? arithmetic logic unit ..............................................................................10 3.4 status register .................................................................................................11 3.5 general purpose register file .........................................................................12 3.6 stack pointer ....................................................................................................14 3.7 instruction execution timing .............................................................................14 3.8 reset and interrupt handling ............................................................................15 4 memories ............... .............. .............. ............... .............. .............. .......... 18 4.1 in-system reprogrammabl e flash program memory ......................................18 4.2 sram data memory .........................................................................................19 4.3 eeprom data memory ... ................. ................ ............. ............ ............. ..........22 4.4 i/o memory .......................................................................................................27 4.5 external memory interface ................................................................................27 4.6 general purpose i/o registers ............ .............................................................36 5 system clock ........... ................ ................ ................. ................ ............. 37 5.1 clock systems and their distribution ... .............................................................37 5.2 clock sources ...................................................................................................38 5.3 default clock source ........................................................................................38 5.4 crystal oscillator ...............................................................................................39 5.5 low-frequency crystal oscillator ......................................................................40 5.6 calibrated internal rc o scillator ......................................................................41 5.7 external clock ...................................................................................................42 5.8 clock output buffer ..........................................................................................43 422 7679h?can?08/08 at90can32/64/128 5.9 timer/counter2 oscillator .................................................................................43 5.10 system clock prescaler ....................................................................................44 6 power management and sleep modes ........... .............. .............. .......... 46 6.1 idle mode ..........................................................................................................47 6.2 adc noise reduction mode .............................................................................47 6.3 power-down mode ............................................................................................47 6.4 power-save mode .............................................................................................47 6.5 standby mode ...................................................................................................48 6.6 minimizing power consumption .......................................................................48 7 system control and reset .... .............. .............. .............. .............. ........ 51 7.1 reset ................................................................................................................51 7.2 internal voltage reference ...............................................................................56 7.3 watchdog timer ...............................................................................................57 7.4 timed sequences for changing the configuration of the watchdog timer .....59 8 interrupts ............... .............. .............. ............... .............. .............. .......... 60 8.1 interrupt vectors in at90can32/64/128 ..........................................................60 8.2 moving interrupts between application and boot space ..................................64 9 i/o-ports ............... ................ .............. ............... .............. .............. .......... 66 9.1 introduction .......................................................................................................66 9.2 ports as general digital i/o ..............................................................................67 9.3 alternate port functions ...................................................................................71 9.4 register description for i/o-ports .....................................................................89 10 external interrupts .......... ................ ................. .............. .............. .......... 93 10.1 external interrupt register description .............................................................93 11 timer/counter3/1/0 prescaler s ........... .............. .............. .............. ........ 96 11.1 overview ...........................................................................................................96 11.2 timer/counter0/1/3 pres calers register description .......................................98 12 8-bit timer/counter0 with pw m .............. ................. ................ ............. 99 12.1 features ............................................................................................................99 12.2 overview ...........................................................................................................99 12.3 timer/counter clock sources .........................................................................100 12.4 counter unit ....................................................................................................100 12.5 output compare unit ......................................................................................101 12.6 compare match output unit ...........................................................................103 423 7679h?can?08/08 at90can32/64/128 12.7 modes of operation ........................................................................................104 12.8 timer/counter timing dia grams .....................................................................108 12.9 8-bit timer/counter register description .......................................................109 13 16-bit timer/counter (timer/counter1 and timer/counter3) ........... 113 13.1 features ..........................................................................................................113 13.2 overview .........................................................................................................113 13.3 accessing 16-bit registers .............................................................................116 13.4 timer/counter clock sources .........................................................................119 13.5 counter unit ....................................................................................................120 13.6 input capture unit ...........................................................................................121 13.7 output compare units ....................................................................................123 13.8 compare match output unit ...........................................................................125 13.9 modes of operation ........................................................................................126 13.10 timer/counter timing diagrams .......... ...........................................................134 13.11 16-bit timer/counter re gister description .....................................................135 14 8-bit timer/counter2 with pwm a nd asynchronous operation ...... 145 14.1 features ..........................................................................................................145 14.2 overview .........................................................................................................145 14.3 timer/counter clock sources .........................................................................147 14.4 counter unit ....................................................................................................147 14.5 output compare unit ......................................................................................148 14.6 compare match output unit ...........................................................................149 14.7 modes of operation ........................................................................................150 14.8 timer/counter timing dia grams .....................................................................155 14.9 8-bit timer/counter register description .......................................................157 14.10 asynchronous operation of the timer/ counter2 .............................................160 14.11 timer/counter2 prescaler ...............................................................................163 15 output compare modulator - ocm ......... ................. ................ ........... 165 15.1 overview .........................................................................................................165 15.2 description ......................................................................................................165 16 serial peripheral interface ? spi ......... .............. .............. ............ ........ 168 16.1 features ..........................................................................................................168 16.2 ss pin functionality ........................................................................................172 16.3 data modes ....................................................................................................175 424 7679h?can?08/08 at90can32/64/128 17 usart (usart0 and usart1) ................. ................ .............. ........... 177 17.1 features ..........................................................................................................177 17.2 overview .........................................................................................................177 17.3 dual usart ...................................................................................................177 17.4 clock generation ............................................................................................179 17.5 serial frame ...................................................................................................181 17.6 usart initialization ........................................................................................182 17.7 data transmission ? usart transmitte r ......................................................183 17.8 data reception ? usart receiver ................................................................186 17.9 asynchronous data reception .......................................................................190 17.10 multi-processor communic ation mode ...........................................................193 17.11 usart register description ..........................................................................195 17.12 examples of baud rate setting ......................................................................200 18 two-wire serial interface .. .............. .............. .............. .............. ........... 204 18.1 features ..........................................................................................................204 18.2 two-wire serial interface bus definition .........................................................204 18.3 data transfer and frame format ...................................................................205 18.4 multi-master bus systems, arbitratio n and synchronization ..........................207 18.5 overview of the twi module ..........................................................................209 18.6 twi register description .................. ..............................................................212 18.7 using the twi .................................................................................................215 18.8 transmission modes .......................................................................................218 18.9 multi-master systems and arbitration .............................................................232 19 controller area network - ca n ............. ................. ................ ............. 234 19.1 features ..........................................................................................................234 19.2 can protocol ..................................................................................................234 19.3 can controller ................................................................................................240 19.4 can channel ..................................................................................................241 19.5 message objects ............................................................................................243 19.6 can timer ......................................................................................................247 19.7 error management ..........................................................................................248 19.8 interrupts .........................................................................................................249 19.9 can register description ...............................................................................251 19.10 general can registers ..................................................................................252 19.11 mob registers ................................................................................................261 425 7679h?can?08/08 at90can32/64/128 19.12 examples of can baud rate setting .. ...........................................................266 20 analog comparator .......... .............. .............. .............. .............. ........... 269 20.1 overview .........................................................................................................269 20.2 analog comparator register description .......................................................269 20.3 analog comparator multiplexed input ............................................................271 21 analog to digital converte r - adc .............. .............. .............. ........... 273 21.1 features ..........................................................................................................273 21.2 operation ........................................................................................................274 21.3 starting a conversion .....................................................................................275 21.4 prescaling and conversion timing .................................................................276 21.5 changing channel or reference selection ....................................................279 21.6 adc noise canceler .......................................................................................280 21.7 adc conversion result ..................................................................................284 21.8 adc register description ...............................................................................287 22 jtag interface and on-chip debug system ................... .................. 293 22.1 features ..........................................................................................................293 22.2 overview .........................................................................................................293 22.3 test access port ? tap ..................................................................................293 22.4 tap controller ................................................................................................296 22.5 using the boundary-scan chain .....................................................................297 22.6 using the on-chip debug system ..................................................................297 22.7 on-chip debug specific jtag instructions ....................................................298 22.8 on-chip debug related register in i/o memory ............................................299 22.9 using the jtag programming capabilitie s ....................................................299 22.10 bibliography ....................................................................................................299 23 boundary-scan ieee 1149.1 (jtag) .......... ................ .............. ........... 300 23.1 features ..........................................................................................................300 23.2 system overview ............................................................................................300 23.3 data registers ................................................................................................300 23.4 boundary-scan specific jtag instructions ....................................................302 23.5 boundary-scan related register in i/ o memory ............................................304 23.6 boundary-scan chain .....................................................................................304 23.7 at90can32/64/128 boundary-scan order ............ ........................................314 23.8 boundary-scan description language files ...................................................320 426 7679h?can?08/08 at90can32/64/128 24 boot loader support ? read-while-w rite self-programming ......... 321 24.1 features ..........................................................................................................321 24.2 application and boot loader flash sections ..................................................321 24.3 read-while-write and no read-while-write flash sections .........................321 24.4 boot loader lock bits .....................................................................................324 24.5 entering the boot loader program .................................................................325 24.6 addressing the flash during self-progr amming ............................................327 24.7 self-programming the flash ...........................................................................328 25 memory programming ........ .............. ............... .............. .............. ........ 336 25.1 program and data memory lock bits .............................................................336 25.2 fuse bits .........................................................................................................337 25.3 signature bytes ..............................................................................................339 25.4 calibration byte ..............................................................................................339 25.5 parallel programming overview .....................................................................339 25.6 parallel programming .....................................................................................342 25.7 spi serial programming overview ...... ...........................................................348 25.8 spi serial programming .................................................................................349 25.9 jtag programming overview ............. ...........................................................352 26 electrical characteristics (1) ............................................................................................... 365 26.1 absolute maximum rating s* ...........................................................................365 26.2 dc characteristics ..........................................................................................366 26.3 external clock drive characteristics ..............................................................367 26.4 maximum speed vs. vcc ...............................................................................368 26.5 two-wire serial interface characteristics .......................................................369 26.6 spi timing characteristics .............................................................................370 26.7 can physical layer characteristics ...............................................................372 26.8 adc characteristics .......................................................................................373 26.9 external data memory characteristics ...........................................................375 26.10 parallel programming characteristics ............................................................380 27 decoupling capacitors ....... .............. ............... .............. .............. ........ 383 28 at90can32/64/128 typical ch aracteristics ............. .............. ........... 384 28.1 active supply current .....................................................................................384 28.2 idle supply current .........................................................................................387 28.3 power-down supply curr ent ...........................................................................389 28.4 power-save supply current ............................................................................390 427 7679h?can?08/08 at90can32/64/128 28.5 standby supply current ..................................................................................391 28.6 pin pull-up ......................................................................................................391 28.7 pin driver strength .........................................................................................393 28.8 pin thresholds and hysteresis .......................................................................395 28.9 bod thresholds and analog comparator offset ...........................................397 28.10 internal oscillator speed ................................................................................399 28.11 current consumption of peripheral units .......................................................401 28.12 current consumption in reset and re set pulse width ..................................403 29 register summary ............ .............. .............. .............. .............. ........... 405 30 instruction set summary ... .............. ............... .............. .............. ........ 409 31 ordering information .......... .............. ............... .............. .............. ........ 412 32 packaging information ....... .............. ............... .............. .............. ........ 412 32.1 tqfp64 ..........................................................................................................413 32.2 qfn64 ............................................................................................................414 33 errata ........... ................ ................ ................. ................ .............. ........... 416 33.1 errata summary ............ ..................................................................................416 33.2 errata description ...........................................................................................416 34 datasheet revision history for at90 can32/64/128 ....... .................. 420 34.1 changes from 7679g - 03/08 to 7679h - 08/08 .............................................420 34.2 changes from 7679f - 11/07 to 7679g - 03/08 ..............................................420 34.3 changes from 7679e - 07/07 to 7679f - 11/07 ..............................................420 34.4 changes from 7679d - 02/07 to 7679e - 07/07 ..............................................420 34.5 changes from 7679c - 01/07 to 7679d - 02/07 ..............................................420 34.6 changes from 7679b - 11/06 to 7679c - 01/07 ..............................................420 34.7 changes from 7679a - 10/06 to 7679b - 11/06 ..............................................420 34.8 document creation .........................................................................................420 7679h?can?08/08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection wi th atmel products. no license, expr ess or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including , but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indire ct, consequential, punitive, special or i nciden- tal damages (including, without li mitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of th is document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2008 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other te rms and product names may be trademarks of others. |
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